Abstract: A computer processor protects a protected word in computer readable memory by employing a canary word in the same buffer as the protected word that is protected by a secure bit and/or by employing a canary bit that directly protects the protected word. A bit setting module marks the protected word as tainted by setting the secure bit or canary bit in response to overwrite of the canary word and/or protected word, including overwrite resulting from overflow of the buffer. A validation module validates non-control data stored in the protected word every time the non-control data is used by a computer process by checking the secure bit of the canary word and/or by checking the canary bit of the protected word.

Abstract: Prevention of buffer-overflow attacks on a computer system is presented. In another aspect of the present invention, a Secure Bit is associated with a memory location. A further aspect of the present invention involves modification of semantics to manage the Secure Bit. When the Secure Bit is marked, an interrupt or fault signal is generated.

Abstract: This application relates to a micro-fastening system and, more particularly, to a mechanical micro-fastening system employing a plurality of mating nanoscale fastening elements (16, 18) and a method of manufacturing a micro-fastening system. The mating nanoscale fastening elements (16, 18) are formed by functionalizing nanotubes having an ordered array of hexagons with pentagons and heptagons at particular heterojunctions.

Abstract: Nanomechanisms are employed in nanomemory elements which, in turn, are employable in nanoscale memory devices. A nanoscale particle is enclosed within a nonocapsule to create a bistable device which is both readable and writable in a variety of ways. A nonamechanism for use in a nanoscale memory element includes a first element in the form of a nanoassembly having a cavity and second element in the form of a nanostructure which is removeably disposed within the cavity. In one embodiment, the nanoassembly is demonstrated as a C480 capsule and the nanostructure is demonstrated as a charged hd 60 fullerene molecule. The nanoscale memory devices combine high switching speed, high packing density and stability with non0volatility of the stored data.

Abstract: The present invention relates to nanomechanisms (10) employed in nanomemory elements (30) which, in turn, are employable in nanoscale memory devices (50). The nanoscale memory devices combine high switching speed, high packing density and stability with non-volatility of the stored data.