Patents by Inventor Richard Ernest Demaray
Richard Ernest Demaray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160181066Abstract: Systems and methods using PVD for producing materials, for example nitrides, are disclosed. The present application also relates to use of the materials for electrode materials.Type: ApplicationFiled: October 16, 2013Publication date: June 23, 2016Inventors: Daniel Brors, Richard Ernest DeMaray, David Slutz, Richard Clark
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Patent number: 8173482Abstract: Methods for protecting a cadmium sulfide layer on a substrate are provided. The method can include sputtering a cadmium sulfide layer onto a substrate from a cadmium sulfide target at a sputtering pressure (e.g., about 10 mTorr to about 150 mTorr), and sputtering a cap layer directly on the cadmium sulfide layer. The cap layer can be sputtered directly onto the cadmium sulfide layer without breaking vacuum of the sputtering pressure. Methods are also provided for manufacturing a cadmium telluride based thin film photovoltaic device through depositing a cadmium sulfide layer on a substrate, depositing a cap layer directly on the cadmium sulfide layer, heating the substrate to sublimate at least a portion of the cap layer from the cadmium sulfide layer, and then depositing a cadmium telluride layer on the cadmium sulfide layer. An intermediate substrate for forming a cadmium telluride based thin-film photovoltaic device is also provided.Type: GrantFiled: April 30, 2010Date of Patent: May 8, 2012Assignee: PrimeStar Solar, Inc.Inventors: Jennifer Ann Drayton, Richard Ernest Demaray
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Publication number: 20110269261Abstract: Methods for protecting a cadmium sulfide layer on a substrate are provided. The method can include sputtering a cadmium sulfide layer onto a substrate from a cadmium sulfide target at a sputtering pressure (e.g., about 10 mTorr to about 150 mTorr), and sputtering a cap layer directly on the cadmium sulfide layer. The cap layer can be sputtered directly onto the cadmium sulfide layer without breaking vacuum of the sputtering pressure. Methods are also provided for manufacturing a cadmium telluride based thin film photovoltaic device through depositing a cadmium sulfide layer on a substrate, depositing a cap layer directly on the cadmium sulfide layer, heating the substrate to sublimate at least a portion of the cap layer from the cadmium sulfide layer, and then depositing a cadmium telluride layer on the cadmium sulfide layer. An intermediate substrate for forming a cadmium telluride based thin-film photovoltaic device is also provided.Type: ApplicationFiled: April 30, 2010Publication date: November 3, 2011Applicant: PRIMESTAR SOLAR, INC.Inventors: Jennifer Ann Drayton, Richard Ernest Demaray
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Patent number: 6821562Abstract: In accordance with the present invention, an insulating sealing structure useful in physical vapor deposition apparatus is provided. The insulating sealing structure is capable of functioning under high vacuum and high temperature conditions. The apparatus is a three dimensional structure having a specifically defined range of electrical, chemical, mechanical and thermal properties enabling the structure to function adequately as an insulator which does not break down at voltages ranging between about 1,500 V and about 3,000 V, which provides a seal against a vacuum of at least about 10−6 Torr, and which can function at a continuous operating temperature of about 300° F. (148.9° C.) or greater.Type: GrantFiled: June 25, 2002Date of Patent: November 23, 2004Assignee: Applied Materials, Inc.Inventors: Richard Ernest Demaray, Manuel J. Herrera, David F. Eline, Chandra Deshpandey
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Publication number: 20020187271Abstract: In accordance with the present invention, an insulating sealing structure useful in physical vapor deposition apparatus is provided. The insulating sealing structure is capable of functioning under high vacuum and high temperature conditions. The apparatus is a three dimensional structure having a specifically defined range of electrical, chemical, mechanical and thermal properties enabling the structure to function adequately as an insulator which does not break down at voltages ranging between about 1,500 V and about 3,000 V, which provides a seal against a vacuum of at least about 10−6 Torr, and which can function at a continuous operating temperature of about 300° F. (148.9° C.) or greater.Type: ApplicationFiled: June 25, 2002Publication date: December 12, 2002Inventors: Richard Ernest Demaray, Manuel J. Herrera, David F. Eline, Chandra Deshpandey
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Patent number: 6436509Abstract: In accordance with the present invention, an insulating sealing structure useful in physical vapor deposition apparatus is provided. The insulating sealing structure is capable of functioning under high vacuum and high temperature conditions. The apparatus is a three dimensional structure having a specifically defined range of electrical, chemical, mechanical and thermal properties enabling the structure to function adequately as an insulator which does not break down at voltages ranging between about 1,500 V and about 3,000 V, which provides a seal against a vacuum of at least about 10−6 Torr, and which can function at a continuous operating temperature of about 300° F. (148.9° C.) or greater.Type: GrantFiled: January 6, 2000Date of Patent: August 20, 2002Assignee: Applied Materials, Inc.Inventors: Richard Ernest Demaray, Manuel J. Herrera, David F. Eline, Chandra Deshpandey
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Patent number: 6362097Abstract: Thin semiconductor films or layers having a pre-selected degree of crystallinity, from amorphous material to poly-crystalline material, can be obtained by selecting an appropriate aspect ratio for a collimator used during a sputtering process. The orientation of the deposited film also can be tailored by selection of the collimator aspect ratio. Sputtered collimation permits highly crystalline films to be formed at temperatures significantly below the annealing temperature of the sputtered material. Thus, required fabrication steps and increase the throughput of the use of low temperatures allows films of substantially greater crystallinity and carrier mobility to be fabricated on glass and other low temperature substrates. Additionally, thin semiconductor Trapped charge defects also can be reduced by grounding the collimator to provide electrical isolation between the charged plasma particles and the substrate on which the sputtered layer is to be formed.Type: GrantFiled: July 14, 1998Date of Patent: March 26, 2002Assignee: Applied Komatsu Technlology, Inc.Inventors: Richard Ernest Demaray, Chandra Deshpandey, Rajiv Gopal Pethe
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Patent number: 6257045Abstract: Automated systems and methods for processing substrates are described. An automated processing system includes: a vacuum chamber; a substrate support located inside the vacuum chamber and constructed and arranged to support a substrate during processing; and a substrate alignment detector constructed and arranged to detect if the substrate is misaligned as the substrate is transferred into the vacuum chamber based upon a change in a physical condition inside the system. The substrate alignment detector may include a vibration detector coupled to the substrate support. A substrate may be transferred into the vacuum chamber. The position of the substrate may be recorded as it is being transferred into the vacuum chamber. Misalignment of the substrate with respect to the substrate support may be detected. The substrate may be processed. The processed substrate may be unloaded from the vacuum chamber. The position of the processed substrate may be recorded as it is being unloaded from the vacuum chamber.Type: GrantFiled: September 8, 1999Date of Patent: July 10, 2001Assignee: Applied Komatsu Technology, Inc.Inventors: Akihiro Hosokawa, Richard Ernest Demaray, Makoto Inagawa, Ravi Mullapudi, Harlan L. Halsey, Michael T. Starr
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Patent number: 6205870Abstract: Automated systems and methods for processing substrates are described. An automated processing system includes: a vacuum chamber; a substrate support located inside the vacuum chamber and constructed and arranged to support a substrate during processing; and a substrate alignment detector constructed and arranged to detect if the substrate is misaligned as the substrate is transferred into the vacuum chamber based upon a change in a physical condition inside the system. The substrate alignment detector may include a vibration detector coupled to the substrate support. A substrate may be transferred into the vacuum chamber. The position of the substrate may be recorded as it is being transferred into the vacuum chamber. Misalignment of the substrate with respect to the substrate support may be detected. The substrate may be processed. The processed substrate may be unloaded from the vacuum chamber. The position of the processed substrate may be recorded as it is being unloaded from the vacuum chamber.Type: GrantFiled: October 10, 1997Date of Patent: March 27, 2001Assignee: Applied Komatsu Technology, Inc.Inventors: Akihiro Hosokawa, Richard Ernest Demaray, Makoto Inagawa, Ravi Mullapudi, Harlan L. Halsey, Michael T. Starr
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Patent number: 6033483Abstract: In accordance with the present invention, an insulating sealing structure useful in physical vapor deposition apparatus is provided. The insulating sealing structure is capable of functioning under high vacuum and high temperature conditions. The apparatus is a three dimensional structure having a specifically defined range of electrical, chemical, mechanical and thermal properties enabling the structure to function adequately as an insulator which does not break down at voltages ranging between about 1,500 V and about 3,000 V, which provides a seal against a vacuum of at least about 10.sup.-6 Torr, and which can function at a continuous operating temperature of about 300.degree. F. (148.9.degree. C.) or greater.Type: GrantFiled: July 24, 1997Date of Patent: March 7, 2000Assignee: Applied Materials, Inc.Inventors: Richard Ernest Demaray, Manuel J. Herrera, David F. Eline, Chandra Deshpandey
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Patent number: 5799860Abstract: A sputtering target assembly is fabricated by diffusion bonding a target material plate to a backing plate. The plates are cleaned in a vacuum environment, and an interlayer is formed on one or more of the plates. The plates are then joined under heat and pressure, before an oxide layer can form on the joining surfaces of the plates. The plates may be sequentially processed through cleaning, interlayer deposition, and bonding chambers, all with vacuum environments, to form the finished part, or, a single chamber may be used to provide the cleaning, interlayer deposition and bonding functions.Type: GrantFiled: August 7, 1995Date of Patent: September 1, 1998Assignee: Applied Materials, Inc.Inventors: Richard Ernest Demaray, Akihiro Hosokawa, Manuel J. Herrera
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Patent number: 5676803Abstract: A target, target backing plate, and cover plate form a target plate assembly. The sputtering target assembly includes an integral cooling passage. A series of grooves are constructed in either the target backing plate or the target backing cooling cover plate, which are then securely bonded to one another. The sputtering target can be a single monolith with a target backing plate or can be securely attached to the target backing plate by one of any number of conventional bonding methods. Tantalum to titanium, titanium to titanium and aluminum to titanium, diffusion bonding can be used.The target plate assembly completely covers and seals against a top opening of a sputtering processing chamber. Cooling liquid connections are provided only from the perimeter of the target assembly. When a top vacuum chamber seals the side opposite the pressure chamber, the pressure on both sides of the target assembly is nearly equalized.Type: GrantFiled: January 21, 1997Date of Patent: October 14, 1997Inventors: Richard Ernest Demaray, Manuel Herrera, David E. Berkstresser