Patents by Inventor Richard Eugene Kessler

Richard Eugene Kessler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10846239
    Abstract: A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 24, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Michael Bertone
  • Patent number: 10782896
    Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 22, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
  • Publication number: 20200174945
    Abstract: A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Michael Bertone
  • Patent number: 10599430
    Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 24, 2020
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10599437
    Abstract: A predicted branch result is determined based on at least a portion of branch prediction information, which is updated based on an actual branch result, which is provided based on an executed branch instruction. For a first execution of a first branch instruction, the updating includes: computing a randomized value and storing the randomized value in association with an identified subset of one or more contexts that includes a context associated with the first branch instruction, obfuscating the actual branch result based at least in part on the randomized value, and storing a resulting obfuscated value in the branch prediction information. Providing a predicted branch result for a second execution of the first branch instruction includes: retrieving the obfuscated value from the branch prediction information, retrieving the randomized value, and de-obfuscating the obfuscated value using the randomized value to recover the actual branch result as the predicted branch result.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 24, 2020
    Assignee: Marvell World Trade Ltd.
    Inventors: Richard Eugene Kessler, Wilson P. Snyder, II, Shubhendu Sekhar Mukherjee
  • Patent number: 10599577
    Abstract: Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of a first processor core should be admitted into the shared resource based at least in part on the stored admission control information; and updating the admission control information based on a latency of a response to a particular memory access request admitted into the shared resource, where the updating depends on whether the response originated from a particular cache level included in the shared resource or from the main memory.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 24, 2020
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson, Richard Eugene Kessler, Wilson Snyder
  • Patent number: 10540181
    Abstract: Instructions are executed in a pipeline of a processor, where each instruction is associated with a particular context. A first storage stores branch prediction information characterizing results of branch instructions previously executed. The first storage is dynamically partitioned into partitions of one or more entries. Dynamically partitioning includes updating a partition to include an additional entry by associating the additional entry with a particular subset of one or more contexts. A predicted branch result is determined based on at least a portion of the branch prediction information. An actual branch result provided based on an executed branch instruction is used to update the branch prediction information. Providing a predicted branch result for a first branch instruction includes retrieving a first entry from a first partition based at least in part on an identified first subset of one or more contexts associated with the first branch instruction.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 21, 2020
    Assignee: Marvell World Trade Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, David Kravitz, Edward McLellan, Rabin Sugumar
  • Patent number: 10445096
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20190227802
    Abstract: A predicted branch result is determined based on at least a portion of branch prediction information, which is updated based on an actual branch result, which is provided based on an executed branch instruction. For a first execution of a first branch instruction, the updating includes: computing a randomized value and storing the randomized value in association with an identified subset of one or more contexts that includes a context associated with the first branch instruction, obfuscating the actual branch result based at least in part on the randomized value, and storing a resulting obfuscated value in the branch prediction information. Providing a predicted branch result for a second execution of the first branch instruction includes: retrieving the obfuscated value from the branch prediction information, retrieving the randomized value, and de-obfuscating the obfuscated value using the randomized value to recover the actual branch result as the predicted branch result.
    Type: Application
    Filed: April 26, 2018
    Publication date: July 25, 2019
    Inventors: Richard Eugene KESSLER, Wilson P. SNYDER, II, Shubhendu Sekhar MUKHERJEE
  • Publication number: 20190227803
    Abstract: Instructions are executed in a pipeline of a processor, where each instruction is associated with a particular context. A first storage stores branch prediction information characterizing results of branch instructions previously executed. The first storage is dynamically partitioned into partitions of one or more entries. Dynamically partitioning includes updating a partition to include an additional entry by associating the additional entry with a particular subset of one or more contexts. A predicted branch result is determined based on at least a portion of the branch prediction information. An actual branch result provided based on an executed branch instruction is used to update the branch prediction information. Providing a predicted branch result for a first branch instruction includes retrieving a first entry from a first partition based at least in part on an identified first subset of one or more contexts associated with the first branch instruction.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Shubhendu Sekhar MUKHERJEE, Richard Eugene KESSLER, David KRAVITZ, Edward MCLELLAN, Rabin SUGUMAR
  • Patent number: 10331500
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 25, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20190138232
    Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
  • Patent number: 10248420
    Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 2, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10216430
    Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 26, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
  • Publication number: 20180293100
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293114
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
    Type: Application
    Filed: September 7, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293070
    Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293113
    Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10084719
    Abstract: A new approach is proposed that contemplates systems and methods to support hardware-based Quality of Service (QoS) operations, which offloads metering functionalities under OpenFlow protocol to a programmable hardware unit/block/component. The hardware unit supports several hardware implemented ports and each port supports multiple configurable queues for the packet flows through a network switch/chip/system. Specifically, the hardware unit includes a plurality of descriptor queues (DQs) configured to accept requests to send a plurality of packets from one or more CPU cores, and a plurality of condition and schedule modules configured to meter, schedule, and condition the packets through a hierarchy of scheduling queues under one or more metering constraints.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 25, 2018
    Assignee: Cavium, Inc.
    Inventors: Muhammad Raghib Hussain, Vishal Murgai, Manojkumar Panicker, Faisal Masood, Richard Eugene Kessler
  • Patent number: 10002218
    Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 19, 2018
    Assignee: Cavium, Inc.
    Inventors: Shahid Ikram, Isam Akkawi, Richard Eugene Kessler, James Ellis, David Asher