Abstract: Apparatus comprises source circuitry to provide data items; buffer circuitry having a set of buffer entries to hold one or more data items, provided by the source circuitry, for delivery to one or more destinations within a respective delivery latency, in which a buffer entry holding an initial data item becomes available to hold another data item in response to delivery of the initial data item to its respective destination; and control circuitry to control acceptance of data items from the source circuitry for holding by the buffer circuitry, the control circuitry being configured to control the buffer circuitry to accept a given data item when: (i) a buffer entry is available to hold the given data item and (ii) the delivery latency of data items including the given data item held by the buffer circuitry is such that at least a threshold number of buffer entries may be made available within no more than a threshold availability period.

Abstract: Apparatus comprises source circuitry to provide data items; buffer circuitry having a set of buffer entries to hold one or more data items, provided by the source circuitry, for delivery to one or more destinations within a respective delivery latency, in which a buffer entry holding an initial data item becomes available to hold another data item in response to delivery of the initial data item to its respective destination; and control circuitry to control acceptance of data items from the source circuitry for holding by the buffer circuitry, the control circuitry being configured to control the buffer circuitry to accept a given data item when: (i) a buffer entry is available to hold the given data item and (ii) the delivery latency of data items including the given data item held by the buffer circuitry is such that at least a threshold number of buffer entries may be made available within no more than a threshold availability period.

Abstract: An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.

Abstract: An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

Abstract: An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address.

Abstract: An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address.

Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data.

Abstract: An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of entries for storing data, and allocation circuitry, responsive to a trigger event for allocating new data into the storage structure, to determine a victim entry into which the new data is to be stored, and to allocate the new data into the victim entry upon determining that the new data is available. Conflict detection circuitry is used to detect when the new data will conflict with data stored in one or more entries of the storage structure, and to cause the data in said one or more entries to be invalidated. The conflict detection circuitry is arranged to perform, prior to a portion of the new data required for conflict detection being available, at least one initial stage detection operation to determine, based on an available portion of the new data, candidate entries whose data may conflict with the new data.

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.