Patents by Inventor Richard F. Grafton

Richard F. Grafton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9804942
    Abstract: In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 31, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: John A. Hayden, Richard F. Grafton, Matthew Puzey, Gordon Cheung, James Frank Galeotos
  • Publication number: 20160349326
    Abstract: A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.
    Type: Application
    Filed: May 26, 2015
    Publication date: December 1, 2016
    Applicant: ANALOG DEVICES GLOBAL
    Inventors: Richard F. Grafton, Chad R. Wentworth, Yashwanth Nagaraja
  • Publication number: 20160350240
    Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Applicant: ANALOG DEVICES GLOBAL
    Inventors: Richard F. Grafton, Shivakumar Patil, James Potts, Lewis F. Lahr
  • Patent number: 9390043
    Abstract: Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 12, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Richard F. Grafton, John M. Young, David J. Katz
  • Patent number: 9268970
    Abstract: A security-aware master is provided, such that a master can determine its security state before attempting access to secure resources or before requesting secure access level. An exemplary system include a system interconnect; one or more masters coupled with the system interconnect; and a master security check register coupled with the system interconnect. The master security check register is configured to receive a request from a master via the system interconnect to access the master security check register, wherein the request includes a master operating state signal that indicates a security state of the master requesting access, and return a data value to the master based on the master operating state signal, wherein the data value indicates a current security state of the master requesting access.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 23, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventor: Richard F. Grafton
  • Publication number: 20150355989
    Abstract: In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.
    Type: Application
    Filed: May 20, 2015
    Publication date: December 10, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: JOHN A. HAYDEN, RICHARD F. GRAFTON, MATTHEW PUZEY, GORDON CHEUNG, JAMES FRANK GALEOTOS
  • Publication number: 20150269396
    Abstract: A security-aware master is provided, such that a master can determine its security state before attempting access to secure resources or before requesting secure access level. An exemplary system include a system interconnect; one or more masters coupled with the system interconnect; and a master security check register coupled with the system interconnect. The master security check register is configured to receive a request from a master via the system interconnect to access the master security check register, wherein the request includes a master operating state signal that indicates a security state of the master requesting access, and return a data value to the master based on the master operating state signal, wherein the data value indicates a current security state of the master requesting access.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 24, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventor: Richard F. Grafton
  • Publication number: 20140173147
    Abstract: Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Inventors: Richard F. Grafton, John M. Young, David J. Katz