Abstract: A distributed engine control system is provided. The engine control system includes first and second engine data concentrators. Each of the first and second engine data concentrators include a processor module, a signal conditioning module coupled to the processor module, a data transfer module coupled to the processor module, and a data bus coupled between the first and second engine data concentrators and a hydro-mechanical unit (HMU).

Abstract: An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.

Abstract: An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.

Abstract: A distributed engine control system is provided. The engine control system includes first and second engine data concentrators. Each of the first and second engine data concentrators include a processor module, a signal conditioning module coupled to the processor module, a data transfer module coupled to the processor module, and a data bus coupled between the first and second engine data concentrators and a hydro-mechanical unit (HMU).

Abstract: A method of playing a blackjack game permits a player to place two wagers, obtaining two blackjack hands, and a bonus wager to participate in a side bet. A dealer deals two up cards for each of the two wagers, and the side bet is resolved by evaluating the 4 up-cards in accordance with a predetermined hierarch of winning poker results. An alternative manner of play includes the dealer's up-card with the 4 up-cards of the player, with resolution obtained utilizing winning 5-card poker results.

Abstract: A memory system for a digital computer includes a non-volatile random access memory for storing past and present values of state variables is immune from electromagnetic transients and other disturbances which can affect the integrity of the memory. Each memory cell is designed with an energy storage device and logic devices which control the logic sequence for charging of the energy storing devices. These memory cells are aligned in an array and specially designed system is included with this that takes into account the length of time required in order to charge each cell in the array.

Abstract: In a computer system having fault recoverable capability, there is included a first and second data processing unit (DPU), wherein each of the first and second DPU is executing the same task essentially in parallel. Each DPU comprises a processor, a memory and a protected memory. The protected memory stores system data, such that the system data stored in the protected memory is immune from transient conditions. Also included is a monitor, which is operatively connected to the monitor of the other DPU. The monitor detects the occurrence of an upset to reinitialize the DPU, the DPU being reinitialized to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

Abstract: A method and apparatus allows fault recovery in a digital computer based control system whereby system upsets induced by external transient noise conditions can be accommodated. A CPU is coupled to its main memory and its I/O interfaces by a common address/data bus, these three elements being susceptible to having data thereon or therein corrupted by transient noise. Also coupled to the bus, but in a hardened environment, are first and second supplemental memories which, under memory control, operate on alternating even and odd computational frames defined by the CPU's real-time clock to store the same words as are then being entered into the CPU's main memory. As computational frames are entered into one or the other of these two memories by eaves-dropping on the common bus, the other supplemental memory is transferring its contents to a backup memory which is also housed in the noise-immune environment.

Abstract: A digital data processor architecture immune from digital computer upset including a non-volatile random access memory for storing past and present values of state variables. An index counter is utilized to offset the store and retrieve instruction base addresses to effect the multiple storage of the state variables in the non-volatile memory. A monitor detects disruptions in data processing and vectors the processor to a reinitialization and restart routine in which the past values of the state variables are utilized.