Patents by Inventor Richard F. Hobson
Richard F. Hobson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8489857Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.Type: GrantFiled: November 5, 2010Date of Patent: July 16, 2013Assignee: Schism Electronics, L.L.C.Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 8190803Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.Type: GrantFiled: December 22, 2008Date of Patent: May 29, 2012Assignee: Schism Electronics, L.L.C.Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Publication number: 20110047354Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.Type: ApplicationFiled: November 5, 2010Publication date: February 24, 2011Applicant: Schism Electronics, L.L.C.Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 7840778Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.Type: GrantFiled: August 31, 2006Date of Patent: November 23, 2010Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Publication number: 20090106468Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.Type: ApplicationFiled: December 22, 2008Publication date: April 23, 2009Applicant: SCHISM ELECTRONICS, L.L.C.Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 7469308Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.Type: GrantFiled: July 31, 2006Date of Patent: December 23, 2008Assignee: Schism Electronics, LLCInventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 7210139Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.Type: GrantFiled: October 20, 2005Date of Patent: April 24, 2007Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 7085866Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.Type: GrantFiled: February 18, 2003Date of Patent: August 1, 2006Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 6959372Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.Type: GrantFiled: February 18, 2003Date of Patent: October 25, 2005Assignee: Cogent Chipware Inc.Inventors: Richard F. Hobson, Bill Ressl, Allan R. Dyck
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Patent number: 5754468Abstract: A new static random access memory cell for standard logic CMOS processes with three or more metal layers is detailed. The method uses three P-type and three N-type MOS transistors to form a two-port memory cell, which can be configured to perform as a one port, or a two port memory cell. In addition to standard memory applications, specialty memories, like a First-In First-Out (FIFO) buffer, which can benefit from the natural 2-port structure of our invention, are particularly appealing. Additional ports can be added for applications like a 3-port microprocessor register array.Type: GrantFiled: June 26, 1996Date of Patent: May 19, 1998Assignee: Simon Fraser UniversityInventor: Richard F. Hobson
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Patent number: RE42145Abstract: An SRAM bit cell with cross-coupled inverters has separate write and read buses. Writing is performed through an NMOS pass transistor. Reading is performed through a PMOS transistor. Because the NMOS transistor does not pass a logic 1 as easily as logic 0, assistance is needed to speed up writing of a logic 1 value relative to the time required to write a logic 0 value. An NMOS pre-charge transistor is coupled between the read bus and ground potential; and, a read is performed simultaneously with a write. This conditions the cell by weakening one of the inverters, such that they cross-couple more quickly when a logic 1 value is written into the cell. Alternatively, a single-ended read/write bus can be coupled to the NMOS pass transistor with write-assistance provided by grounding the PMOS pass transistor.Type: GrantFiled: October 12, 2006Date of Patent: February 15, 2011Inventor: Richard F. Hobson