Patents by Inventor Richard F. Motta
Richard F. Motta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932802Abstract: Various shaped abrasive particles are disclosed. Each shaped abrasive particle includes a body having at least one major surface and a side surface extending from the major surface.Type: GrantFiled: December 2, 2022Date of Patent: March 19, 2024Assignee: SAINT-GOBAIN CERAMICS & PLASTICS, INC.Inventors: Todd M. Cotter, Francois Wagner, Rene G. Demers, Richard J. Klok, Alexandra Marazano, Adam D. Lior, James A. Salvatore, Sujatha K. Iyengar, David F Louapre, Sidath S. Wijesooriya, Ronald Christopher Motta, Gary A. Guertin, Michael D. Kavanaugh, Doruk O. Yener, Jennifer H. Czerepinski, Jun Jia, Frederic Josseaux, Ralph Bauer, Frank J. Csillag, Yang Zhong, James P. Stewart, Mark P. Dombrowski, Sandhya Jayaraman Rukmani, Amandine Martin, Stephen E. Fox, Nilanjan Sarangi, Dean S. Matsumoto
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Patent number: 5656861Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.Type: GrantFiled: May 25, 1995Date of Patent: August 12, 1997Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Tsu-Wei Frank Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-Man Baik, Ting-Pwu Yen
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Patent number: 5620919Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.Type: GrantFiled: March 30, 1995Date of Patent: April 15, 1997Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Frank T.W. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Baik, Ting-Pwu Yen
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Patent number: 5483104Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.Type: GrantFiled: September 28, 1992Date of Patent: January 9, 1996Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-Man Baik, Ting-Pwu Yen
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Patent number: 5172211Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.Type: GrantFiled: January 12, 1990Date of Patent: December 15, 1992Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Frank T. W. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Balk, Ting-Pwu Yen
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Patent number: 5168076Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.Type: GrantFiled: July 1, 1991Date of Patent: December 1, 1992Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Baik, Ting-Pwu Yen
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Patent number: 5166771Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.Type: GrantFiled: January 12, 1990Date of Patent: November 24, 1992Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Baik, Ting-Pwu Yen
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Patent number: 5124774Abstract: A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.Type: GrantFiled: July 19, 1990Date of Patent: June 23, 1992Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-Man Baik, Ting-Pwu Yen