Abstract: A circuit including a sensing circuit, which includes a first delay circuit and a tuning circuit. The tuning circuit includes a sense counter and a reference counter. The sense counter is coupled to the first delay circuit and is configured to count a number of oscillations provided by the first delay circuit and provide a notification to the tuning circuit when the sense counter reaches a threshold value. The reference counter is coupled to the sense counter and a reference clock. The reference counter is configured to store a reference time which represents a time elapsed for the sense counter to reach the threshold value. Also included in the circuit is a second delay circuit coupled to the sensing circuit.

Abstract: Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals.

Abstract: A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes.

Abstract: The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.

Abstract: A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory.