Abstract: A clock recovery circuit includes a phase locked loop in which the control voltage of a voltage controlled oscillator is controlled by a loop filter driven by the output of a phase comparator. During acquisition of the phase locked condition, a frequency error detector is used to detect frequency error and input a frequency error signal to a charge pump circuit associated with the loop filter. Frequency error is detected by a method of determining the phase quadrant of clock signal in which each transition of the data occurs, an algorithm implemented by logic circuit being utilized to selectively generate the frequency error signal only for certain defined transitions between phase quadrant values. Sampling of the phase quadrant values is effected by sampling sub-circuits using latched values of the clock and quadrature clock signals to obtain samples of the clock and quadrature clock signals for each transition, and subsequently determining the phase quadrant value by a logical combination of the samples.