Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.

Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.

Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.