Abstract: A digital signal processor (24) includes a plurality of vector processors (212x), each of which is made up of a group of, for example, six signal processors (214x). Each signal processor includes Local 1 and Local 2 ports (201, 203), and the Local 1 port of one processor of a group is coupled by a path (218) to the Local 2 port of another processor, so the group forms a ring. Each signal processor (214) also includes a memory (234), an arithmetic processor (232), and a switcher (230) for making internal interconnections among the ports, and also includes a switcher control (364, 366). At least one of the signal processors (214) of each group is of a type including a further external port (206), by which data can be coupled by a path (105) to and from the group. The signal processors of each group can be interconnected for serial or parallel processing, all under the control of a group controller (216) associated with each vector processor.

Abstract: A fault tolerant communication arrangement, for switching parallel N-bit information among a plurality of stations, includes an M-bit crossbar switch, where M is greater than N by a number S of supernumerary or spare bit paths. At each station, an interface unit monitors for errors, and when an error is identified to a bit in the transmission path, routes the defective bit to one of the spare bit paths. All stations reroute data from the defective bit path to the same spare bit path. Error coding information is generated at the transmitting interface unit, and transmitted over some of the supernumerary bit paths, and when the number of defective bit paths reduces the number of available supernumerary bit paths to zero, the bit intensity of the error coding is reduced, to free additional supernumerary paths. In a system in which some of the stations include memory, a failure of a memory bit at a particular address is, in effect, a failure of that bit in an overall transmission path.