Patents by Inventor Richard G. DuBose

Richard G. DuBose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7795759
    Abstract: In accordance with various aspects of the present invention, a method and circuit for reducing power consumption of a power strip is provided. In an exemplary embodiment, a power strip is configured for reducing or eliminating power during idle mode by disengaging an outlet from power input. A power strip may include two or more outlets and two or more outlet circuits, with AC power input connected to the outlets through the outlet circuit(s), which may include a current transformer, a control circuit, and a switch. The current transformer secondary winding provides an output power level signal proportional to the outlet load. If behavior of the current transformer secondary winding indicates that the outlet is drawing substantially no power from the AC power input, the switch facilitates disengaging of the current transformer primary from the outlet.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: September 14, 2010
    Assignee: iGo, Inc
    Inventors: Richard G. DuBose, Walter Thornton, Michael D. Heil
  • Patent number: 7779278
    Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: August 17, 2010
    Assignee: iGo, Inc.
    Inventor: Richard G. DuBose
  • Patent number: 7770039
    Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: August 3, 2010
    Assignee: iGo, Inc
    Inventor: Richard G DuBose
  • Publication number: 20100019583
    Abstract: In accordance with various aspects of the present invention, a method and circuit for reducing power consumption of a power module during idle conditions is provided. In an exemplary embodiment, a power module is configured for reducing power during idle mode by disengaging at least one power output from a power input. A power module may include one or more power outputs and one or more power module circuits, with power input connected to the power outputs through the power module circuit(s). The power module circuit may include a current measuring system, a control circuit, and a switch. The current measuring system provides an output power level signal that is proportional to the load at the power output. If current measuring system behavior indicates that a power output is drawing substantially no power from the power input, the switch disengages the power input from the power output.
    Type: Application
    Filed: July 25, 2008
    Publication date: January 28, 2010
    Applicant: IGO, INC.
    Inventors: Richard G. DuBose, Walter Thornton
  • Publication number: 20090322159
    Abstract: In accordance with various aspects of the present invention, a method and circuit for reducing power consumption of a wall plate system during idle conditions is provided. In an exemplary embodiment, a wall plate system is configured for reducing power during idle mode by disengaging at least one outlet from a power input. A wall plate system may include one or more outlets and one or more wall plate circuits, with power input connected to the outlets through the wall plate circuit(s). The wall plate circuit may include a current measuring system, a control circuit, and a switch. The current measuring system provides, through the switch, an output power signal that is proportional to the load at the outlet. If behavior of the current measuring system indicates that an outlet is drawing substantially no power from the power input, the switch disengages the power input from the outlet.
    Type: Application
    Filed: July 25, 2008
    Publication date: December 31, 2009
    Applicant: IGO, INC.
    Inventors: Richard G. DuBose, Walter Thornton
  • Publication number: 20090322160
    Abstract: In accordance with various aspects of the present invention, a method and circuit for reducing power consumption of a power strip is provided. In an exemplary embodiment, a power strip is configured for reducing or eliminating power during idle mode by disengaging an outlet from power input. A power strip may include two or more outlets and two or more outlet circuits, with AC power input connected to the outlets through the outlet circuit(s), which may include a current transformer, a control circuit, and a switch. The current transformer secondary winding provides an output power level signal proportional to the outlet load. If behavior of the current transformer secondary winding indicates that the outlet is drawing substantially no power from the AC power input, the switch facilitates disengaging of the current transformer primary from the outlet.
    Type: Application
    Filed: July 25, 2008
    Publication date: December 31, 2009
    Applicant: IGO, INC.
    Inventors: Richard G. DuBose, Walter Thornton, Michael D. Heil
  • Publication number: 20090300400
    Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.
    Type: Application
    Filed: July 17, 2008
    Publication date: December 3, 2009
    Applicant: IGO, INC.
    Inventor: Richard G. DuBose
  • Publication number: 20090295469
    Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10th to 1/1000th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.
    Type: Application
    Filed: April 3, 2009
    Publication date: December 3, 2009
    Applicant: IGO, INC.
    Inventor: Richard G. DuBose
  • Publication number: 20090287947
    Abstract: A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as 1/10th to 1/1000th of active power, is disclosed. An ultra-low idle power supply may include a primary circuit, a secondary circuit, a switch, and a feedback channel. The secondary circuit is in communication with the primary circuit, and in addition provides feedback to the primary circuit via the feedback channel. The switch receives feedback through the feedback channel and controls the state of the primary circuit. The secondary circuit monitors the output power provided to the electronic device. If the electronic device is drawing little or no power from the ultra-low idle power supply, the secondary circuit facilitates disengaging of the primary circuit. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 19, 2009
    Applicant: IGO, INC.
    Inventor: Richard G. DuBose
  • Patent number: 7554218
    Abstract: A power converter having an aircraft power source detector adapted to limit the amount of power that can be drawn by the power converter when utilized in an aircraft. The power converter may detect an artifact of the aircraft power source, such as the 400 Hz ripple noise on an aircraft power line, or existing in the aircraft cabin, such EMI or aircraft lighting.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: June 30, 2009
    Assignee: iGo, Inc.
    Inventors: Richard G. DuBose, Bryan W. McCoy
  • Publication number: 20090128105
    Abstract: A power converter having an aircraft power source detector configured to limit the amount of power that can be drawn by the power converter when utilized in an aircraft. The power converter may detect an artifact of the aircraft power source, such as the 400 Hz ripple noise on an aircraft power line, or existing in the aircraft cabin, such EMI or aircraft lighting.
    Type: Application
    Filed: December 11, 2008
    Publication date: May 21, 2009
    Inventors: Richard G. DuBose, Bryan W. McCoy
  • Patent number: 5751152
    Abstract: The apparatus includes a first transmitter for transmitting a first test signal from a first end of the cable and a second transmitter for transmitting a second test signal from a second end of the cable. The first test signal is transmitted on a first conductor pair at a first frequency and the second test signal is simultaneously transmitted on a second conductor pair at a second frequency. The apparatus also includes a first receiver for receiving a first coupled signal at the first end of the cable and a second receiver for simultaneously receiving a second coupled signal at the second end of the cable. The first coupled signal exhibits the first frequency and is received on a third conductor pair, while the second coupled signal exhibits the second frequency and is received on a fourth conductor pair. The transmit frequencies are offset such that interference and noise are not detected by the receivers as coupled signals.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: May 12, 1998
    Assignee: Microtest, Inc.
    Inventors: Richard G. DuBose, Martin Teague