Abstract: A description language and a tool for identifying, analyzing and addressing performance issues in event traces. With this language, a behavior descriptor may be defined to describe a simple behavior within a performance trace, by specifying values for a relatively small number of attributes. Even a relatively unsophisticated user can define behavior descriptors, but complex behaviors may be defined based on interactions between multiple behavior descriptors. A trace analysis tool may use a library of behavior descriptors to identify performance issues in performance traces by matching behavior descriptors to the performance trace. This analysis may be used in any number of ways, including reporting to a user detected performance issues reflected in a set of performance traces, filtering a set of performance traces to remove those performance traces corresponding to known performance issues or prioritizing efforts to resolve performance issues.

Abstract: A description language and a tool for identifying, analyzing and addressing performance issues in event traces. With this language, a behavior descriptor may be defined to describe a simple behavior within a performance trace, by specifying values for a relatively small number of attributes. Even a relatively unsophisticated user can define behavior descriptors, but complex behaviors may be defined based on interactions between multiple behavior descriptors. A trace analysis tool may use a library of behavior descriptors to identify performance issues in performance traces by matching behavior descriptors to the performance trace. This analysis may be used in any number of ways, including reporting to a user detected performance issues reflected in a set of performance traces, filtering a set of performance traces to remove those performance traces corresponding to known performance issues or prioritizing efforts to resolve performance issues.

Abstract: A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Abstract: A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Abstract: A system is provided that contains multiple control register and descriptor table register sets so that an execution context switch between X86 protected mode operating systems can be performed with minimal processing overhead. Upon receipt of a protected instruction determined to be a meta-protected instruction, the system calls a meta virtual machine (MVM) that performs the functions necessary to shift execution contexts.

Abstract: The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an “initial state” of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an “initial state” of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer.

Abstract: A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.

Abstract: A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Abstract: A processor-oriented system provides a timer processing engine for supporting multiple virtual minimum time timers. The plurality of virtual minimum time timers of the timer processing engine includes a timer data structure suitable to store timer states of the plurality of virtual minimum time timers. Each timer state may include an elapsed time value, a last time value, a terminal time value, and a set of attributes. The timer states are processed by a timer state machine of the timer processing engine. The plurality of virtual minimum time timers further include a free running counter for providing a current time of the timer processing engine and a comparator for maintaining the timer states. The comparator maintains timer states by performing comparison operations for each virtual minimum time timer. When a virtual minimum time timer reaches a terminal time value, an interrupt generator of the timer processing engine may generate an interrupt.

Abstract: A general purpose dynamically programmable state engine dynamically executes finite state machines and finite state machine models. The state engine includes an input and filter unit, a storage unit, a transition unit, and an action generation unit. The storage unit stores a state entry table including a plurality of state entries. Each state entry in the storage unit includes a state identifier, a symbol identifier, a plurality of state attributes, and a next state. The input and filter unit accepts inputs and translates the inputs to symbols. The symbols are provided to the transition unit. The transition unit maintains a current state and locates a state entry in the storage unit having a state identifier matching the current state and a symbol identifier matching a current symbol. The current state is set to a next state of a matching entry by the transition unit when the matching entry is a terminating entry.

Abstract: A MIB manager including set of software interfaces, semantics, procedures and data structures that work together as a system to dynamically manage a tree of SNMP data objects identified by a standard object identifier (OID) along with each object's value. An agent uses the interface of the MIB manager to add and delete MIB objects by OID. When one or more new objects are added to the MIB tree, the agent provides the MIB manager with references to subroutines within the agent and external to the MIB manager, which subroutines operate to manage the identified objects by monitoring and controlling the objects' values. This enables the MIB manager to be implemented in a manner independent of the application and hardware. The MIB manager allows agent to add new objects at any level within the MIB tree, thus allowing modification at any desired degree of granularity. The agent may add a single leaf element, a table row, an entire table or an entire branch of the MIB tree.

Abstract: A system of composition, apparatuses and process provides for a rapid and reliable development and location of a web fabric structure to position and hold each member of a closely spaced assembly of positioned but not electrically connected units comprising discrete electrical components and integrated circuits in place on a printed circuit board with the external leads or connectors of such units projecting through holes in such circuit board so that such units are held to the circuit board during soldering of those leads to the conductive portions of the printed circuit board and other manipulations. The fabric structure and a coacting masking agent are of such chemical composition that they are readily completely removed from the circuit board and from the units after need for such fabric and masking agent has passed.