Abstract: Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range of precompensation is extended beyond limits imposed by the duty cycle of the clock signal. Catastrophic failure of the write precompensation circuit is prevented by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The range of a write precompensation circuit is extended by ORing the clock and the clock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.

Abstract: The present invention prevents catastrophic failures of a write precompensation circuit from occurring without limiting the precompensation range to a small value and also extends the range of precompensation beyond limits imposed by the duty cycle of the clock signal. The present invention prevents catastrophic failure of the write precompensation circuit by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The present invention extends the range of a write precompensation circuit by ORing the clock and the dock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.

Abstract: A method and apparatus for reducing noise correlation in a partial response channel through optimization of a look-ahead maximum likelihood (ML) detector. In the method of the present invention, the ML detector is optimized in light of the noise correlation generated by the partial response channel. The improved ML detector provides comparable performance to, or better performance than, a Viterbi detector in the presence of colored noise. In the present invention, a set of finite impulse response (FIR) transversal filters are used as the ML estimator for the look-ahead detector. The weighted sum outputs of the FIR filters are compared to a set of thresholds based on previously detected data to make the decision for current detection. The present invention improves the ML detector's performance and reduces its complexity by optimizing the coefficients of the FIR filters in the presence of the correlated or colored noise.

Abstract: An improved Viterbi detector for use in a partial-response maximum-likelihood (PRML) channel. The present invention reduces the amount of hardware necessary in the conventional digital implementation, as well as increasing the speed of the system, by utilizing analog circuits. Whereas prior art analog implementations use more complex hardware and less efficient algorithms, the present invention utilizes easily realizable circuitry to perform a more efficient algorithm. A sampled data Viterbi detector compares a sampled analog input signal with two threshold signals. The binary outputs of the comparing means are then provided to a survival sequence register, as well as being used to formulate new threshold signals for the subsequent input sample. The hardware implements Ferguson's method for calculating sequence metrics by representing the accumulated metric difference as two threshold signals. Probability based decisions are then performed in analog comparators.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.

Abstract: An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm.

Abstract: A maximum likelihood sequence metric calculator for use in a sequence decoder for processing sequences of sampled values from a communication channel or recording device. The metric calculator can be used in a maximum likelihood decoder, where the sequence can be based upon a 2-state trellis. This would include duobinary, dicode, or partial response class IV signalling. The survivor metrics for the two states is proportional to the peak amplitude detected for that state. Thus, the peak amplitude for a state is stored by a peak detector, until an opposite polarity amplitude is detected to switch the trellis path to the opposite polarity state. The path switching threshold to a state is determined by the opposite polarity state's peak amplitude and the maximum likelihood threshold value. Since only the peak amplitude of the state is stored, unbounded metric absolute value growth is not a problem.

Abstract: The present invention describes an improved RLL channel utilizing a closed-loop clock recovery scheme and a simplified decoding algorithm. (1,7) run-length-limited (RLL) code is used to reduce the magnetic nonlinearity problem posed by prior art PRML systems. In the preferred embodiment of the present invention, the analog data signal amplified, filtered and equalized to approximate an ideal waveform. The signal is then sampled and decoded into binary data. The clock recovery circuit is designed to sample the analog data such that the signal peak lies centered between consecutive sample points. It is thus made possible for the phase error to be extracted from a direct comparison of neighboring sample values. The phase error is then used to adjust the clock signal for the following samples. In the decoding algorithm of the present invention, by making useful approximations, the complexity of the decision functions is reduced, along with the number of required look-ahead samples.

Abstract: The present invention is a new design for transconductance elements useful in high-frequency filters such as fully differential state-variable biquads. The present invention enjoys a large dynamic range. It is built with simple circuitry to reduce parasitic capacitance which impedes high-frequency operation. It is easily tunable for use in programmable filters. It is configured in a fully differential circuit and operates on five volts. The present invention is also very useful for implementing dual-input or multiple input transconductance elements. By incorporating additional current sources in the present invention, another degree of freedom is added to the determination of pole frequency and pole quality factors, when the transconductance is used as a biquad filter building block.

Abstract: A temperature compensation control circuit to maintain a constant control gain in an AGC (automatic gain control) amplifier. The present invention compensates for the inherent temperature dependence without using any special processing or non-standard device structures. The present invention utilizes the voltage drop across n diodes in series to produce the control voltage difference (V.sub.C -V.sub.C *). These n series diodes are coupled to the collectors of a PNP emitter coupled pair with emitter resistance. This causes the control voltage difference to be dependent on temperature (nkT/q), but this dependency cancels out with the other inherent temperature dependency in the exponential function of the AGC amplifier which is also produced by a diode form. Thus, the present invention provides temperature compensation with minimum component matching problems and without the need for a PTAT (proportional to absolute temperature) current source.

Abstract: A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period.

Abstract: A high-frequency integrated circuit continuous time low pass filter. An on-chip oscillator is built into the filter. The filter frequency accuracy is established by trimming the frequency of the on-chip oscillator during wafer probe. The oscillator is off during normal operation of the filter. Therefore, the filter does not produce noise that will degrade the performance of the filter during normal operation. After trimming, the filter design is such that accuracy is maintained even during temperature and power supply changes. The adjustment can be made without the oscillator by direct measurement of the filter response.

Abstract: A variable frequency oscillator (VFO) providing a plurality of timing signals set by an external resistor is described. The single external resistor is utilized to set the center frequency of the VFO. The VFO is comprised of a voltage controlled oscillator (VCO), analog divider, and a plurality of current mirrors. The timing currents of the VCO are set by the external resistor and are independent of the control voltage Vc of the VCO. The VFO gain is independent of control voltage for improved control of the open loop gain. The timing voltage swing is inversely proportional to the control voltage but is independent of the timing currents. Current mirrors are coupled to the external resistor and the timing current to provide a plurality of timing signals.

Abstract: Method and apparatus for generating a decode window. A phase locked loop locks a pulse edge of a delayed read data (DRD) signal to an edge of a voltage control oscillator (VCO) clock signal. The edges of the decode window are generated directly from the outer edges of the VCO clock signal. This eliminates errors introduced by quarter cell delay lines, particularly in integrated circuit applications. The transition of the VCO clock signal is used to define a nominal center position coinciding with the mean center position of a data stream. Differential control signals are utilized to shift the VCO transition so that it may be synchronized with the mean bit center position and compensate for non-symmetrical peak jitter. The VCO transition may be shifted without changing the period of the VCO clock signal.