Patents by Inventor Richard Gaggl

Richard Gaggl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230399223
    Abstract: A microphone includes a microelectromechanical system (MEMS) device responsive to sound waves or vibrations having an output coupled to a first node; a programmable gain amplifier or source follower having an input coupled to a second node, and an output for generating an analog signal, wherein the MEMS device output and the programmable gain amplifier or source follower input comprise a first nonlinear equivalent capacitance having a first capacitance-to-voltage (CV) profile; and a nonlinear capacitance component coupled to the first node, the second node, and at least one reference voltage node, wherein the nonlinear capacitance component comprises a second nonlinear equivalent capacitance having a second CV profile.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Wilfried Florian, Niccoló De Milleri, Richard Gaggl, Philipp Greiner, Andreas Wiesbauer
  • Publication number: 20210270872
    Abstract: A readout circuit for resistive and capacitive sensors includes a first input coupled to a reference resistor in a first mode of operation and coupled to a resistive sensor in a second mode of operation; a second input coupled to a capacitive sensor in the first mode of operation and coupled to a reference capacitor in the second mode of operation; and an output for providing a capacitive sensor data stream in the first mode of operation and for providing a resistive sensor data stream in the second mode of operation.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 2, 2021
    Inventors: Richard Gaggl, Andrea Baschirotto, Cesare Buffa, Fulvio Ciciotti
  • Patent number: 11099213
    Abstract: A readout circuit for resistive and capacitive sensors includes a first input coupled to a reference resistor in a first mode of operation and coupled to a resistive sensor in a second mode of operation; a second input coupled to a capacitive sensor in the first mode of operation and coupled to a reference capacitor in the second mode of operation; and an output for providing a capacitive sensor data stream in the first mode of operation and for providing a resistive sensor data stream in the second mode of operation.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 24, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Richard Gaggl, Andrea Baschirotto, Cesare Buffa, Fulvio Ciciotti
  • Patent number: 10685802
    Abstract: In various embodiments, a measuring arrangement is provided. The measuring arrangement may include a micromechanical sensor including a capacitor, a bridge circuit including a plurality of capacitors, at least one capacitor of which is the capacitor of the micromechanical sensor, an amplifier coupled, on the input side, to an output of the bridge circuit, a DC voltage source configured to provide an electrical DC voltage, a chopper including at least one first charge store and a switch structure, The switch structure is configured to couple the first charge store alternately to the DC voltage and the bridge circuit for the purpose of coupling an electrical mixed voltage into the bridge circuit.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 16, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Reinhold, Ulrich Reichold, Richard Gaggl, Andreas Wiesbauer
  • Patent number: 10506318
    Abstract: In accordance with an embodiment, a circuit includes an amplifier and a programmable capacitor coupled between an output of the first non-inverting and the input of the first amplifier.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francesco Polo, Richard Gaggl
  • Patent number: 10326464
    Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Christopher Rogi, Richard Gaggl, Enrique Prefasi
  • Patent number: 10313773
    Abstract: An embodiment amplifier circuit includes a pair of subcircuits that includes a first subcircuit and a second subcircuit, each of which includes a buffer amplifier and a feedback circuit that includes a feedback capacitor. The amplifier circuit also includes a pair of output terminals. The first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals that includes a first output signal and a second output signal. The amplifier circuit is configured for receiving a positive differential input signal at the first subcircuit, receiving a negative differential input signal at the second subcircuit, and receiving the pair of output signals at the pair of output terminals. The amplifier circuit is also configured for transmitting the first output signal to the feedback circuit of the first subcircuit, and transmitting the second output signal to the feedback circuit of the second subcircuit.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 4, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francesco Polo, Richard Gaggl
  • Publication number: 20190120879
    Abstract: A readout circuit for resistive and capacitive sensors includes a first input coupled to a reference resistor in a first mode of operation and coupled to a resistive sensor in a second mode of operation; a second input coupled to a capacitive sensor in the first mode of operation and coupled to a reference capacitor in the second mode of operation; and an output for providing a capacitive sensor data stream in the first mode of operation and for providing a resistive sensor data stream in the second mode of operation.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Inventors: Richard Gaggl, Andrea Baschirotto, Cesare Buffa, Fulvio Ciciotti
  • Patent number: 10250999
    Abstract: A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 2, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francesco Polo, Richard Gaggl, Benno Muehlbacher, Luca Valli
  • Publication number: 20190090066
    Abstract: A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Inventors: Francesco Polo, Richard Gaggl, Benno Muehlbacher, Luca Valli
  • Patent number: 10228414
    Abstract: Sensor devices and methods are provided where a test signal is applied to a capacitive sensor. Furthermore, a bias voltage is applied to the capacitive sensor via a high impedance component. A path for applying the test signal excludes the high impedance component. Using this testing signal, in some implementations a capacity imbalance of the capacitive sensor may be detected.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Cesare Buffa, Richard Gaggl
  • Patent number: 10171916
    Abstract: According to an embodiment, a circuit includes a high-? resistor including a plurality of semiconductor junction devices coupled in series and a plurality of additional capacitances formed in parallel with the plurality of semiconductor junction devices. Each semiconductor junction device of the plurality of semiconductor junction devices includes a parasitic doped well capacitance configured to insert a parasitic zero in a noise transfer function of the high-? resistor. Each additional capacitance of the plurality of additional capacitances is configured to adjust a parasitic pole in the noise transfer function of the high-? resistor in order to compensate for the parasitic zero.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 1, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Luca Valli, Benno Muehlbacher, Richard Gaggl
  • Publication number: 20180337684
    Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 22, 2018
    Inventors: Christopher Rogi, Richard Gaggl, Enrique Prefasi
  • Publication number: 20180332377
    Abstract: In accordance with an embodiment, a circuit includes an amplifier and a programmable capacitor coupled between an output of the first non-inverting and the input of the first amplifier.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Inventors: Francesco Polo, Richard Gaggl
  • Publication number: 20180132024
    Abstract: An embodiment amplifier circuit includes a pair of subcircuits that includes a first subcircuit and a second subcircuit, each of which includes a buffer amplifier and a feedback circuit that includes a feedback capacitor. The amplifier circuit also includes a pair of output terminals. The first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals that includes a first output signal and a second output signal. The amplifier circuit is configured for receiving a positive differential input signal at the first subcircuit, receiving a negative differential input signal at the second subcircuit, and receiving the pair of output signals at the pair of output terminals. The amplifier circuit is also configured for transmitting the first output signal to the feedback circuit of the first subcircuit, and transmitting the second output signal to the feedback circuit of the second subcircuit.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Francesco Polo, Richard Gaggl
  • Patent number: 9866939
    Abstract: An embodiment amplifier circuit includes a pair of subcircuits that includes a first subcircuit and a second subcircuit, each of which includes a buffer amplifier and a feedback circuit that includes a feedback capacitor. The amplifier circuit also includes a pair of output terminals. The first subcircuit and the second subcircuit each generate a different output signal of a pair of output signals that includes a first output signal and a second output signal. The amplifier circuit is configured for receiving a positive differential input signal at the first subcircuit, receiving a negative differential input signal at the second subcircuit, and receiving the pair of output signals at the pair of output terminals. The amplifier circuit is also configured for transmitting the first output signal to the feedback circuit of the first subcircuit, and transmitting the second output signal to the feedback circuit of the second subcircuit.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 9, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francesco Polo, Richard Gaggl
  • Publication number: 20170338069
    Abstract: In various embodiments, a measuring arrangement is provided. The measuring arrangement may include a micromechanical sensor including a capacitor, a bridge circuit including a plurality of capacitors, at least one capacitor of which is the capacitor of the micromechanical sensor, an amplifier coupled, on the input side, to an output of the bridge circuit, a DC voltage source configured to provide an electrical DC voltage, a chopper including at least one first charge store and a switch structure, The switch structure is configured to couple the first charge store alternately to the DC voltage and the bridge circuit for the purpose of coupling an electrical mixed voltage into the bridge circuit.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 23, 2017
    Inventors: Michael Reinhold, Ulrich Reichold, Richard Gaggl, Andreas Wiesbauer
  • Patent number: 9825645
    Abstract: The disclosure is directed to low-power high-resolution analog-to-digital converter (ADCs) circuits implemented with a delta-sigma modulators (DSMs). The DSM includes a single-bit, self-oscillating digital to analog converter (SB-DAC) and a dual-slope integrating quantizer that may replace an N-bit quantizer found in a conventional DSM. The integrating quantizer of this disclosure oscillates after quantization because the SB-DAC in the feedback path directly closes the DSM loop. The integrating quantizer circuit includes a switch at the input and two phases per sample cycle. During the first phase the switch sends an input analog signal to an integrator. During the second phase, the switch sends the feedback signal from the output of the self-oscillating SB-DAC to the integrator. The input to the SB-DAC may be output from a clocked comparator.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Richard Gaggl, Enrique Prefasi, Francisco Javier Perez Sanjurjo, Cesare Buffa
  • Publication number: 20170318393
    Abstract: According to an embodiment, a circuit includes a high-? resistor including a plurality of semiconductor junction devices coupled in series and a plurality of additional capacitances formed in parallel with the plurality of semiconductor junction devices. Each semiconductor junction device of the plurality of semiconductor junction devices includes a parasitic doped well capacitance configured to insert a parasitic zero in a noise transfer function of the high-? resistor. Each additional capacitance of the plurality of additional capacitances is configured to adjust a parasitic pole in the noise transfer function of the high-? resistor in order to compensate for the parasitic zero.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Luca Valli, Benno Muehlbacher, Richard Gaggl
  • Patent number: 9806687
    Abstract: A signal amplification method includes receiving, from a capacitive sensor, a first input signal by a first control terminal of a first transistor, and a second input signal by a first control terminal of a second transistor. The method also includes producing a first output signal, including amplifying a first signal at a first load path terminal of the first transistor using a first inverting amplifier having an output coupled to a resistance network, and producing a second output signal, including amplifying a second signal at a first load path terminal of the second transistor using a second inverting amplifier having an output coupled to the resistance network. The method also includes feeding back the first and second output signal to a second load path terminal of the first transistor and to a second load path terminal of the second transistor via the resistance network according to a pre-determined fraction.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Luca Valli, Benno Muehlbacher, Richard Gaggl