Abstract: A glide controller includes a glide solver and a glide control interface. The glide solver generates at least one vehicular glide schedule including a plurality of discretized targets. The solver generates a plurality of vehicular glide control outputs corresponding to the plurality of discretized targets. The glide control interface outputs the plurality of vehicular glide control outputs, intended to result in a performance adjustment of a vehicle.

Abstract: An elevatier for a vehicular route optimization receives a request for a data point and organizes a configuration file into at least one region that includes at least one spatial data structure index of at least one sub-region which includes the data point. The elevatier constructs at least one polygon using the data point in the at least one sub-region as at least one vertex of the at least one polygon, and searches the configuration file for the at least one spatial data structure index having the at least one polygon that includes the at least one requested data point. The elevatier selects the at least one polygon based on at least one quality condition and interpolates the requested data point using the at least one selected polygon.

Abstract: A vehicular glide solver receives a requested route defined by at least one route parameter. The solver optimizes the requested route using vehicular optimization criteria. The optimization includes analysis of at least one data set pertaining to the requested route, and provides a vehicular glide schedule for discrete points along the requested route in response to the route optimization. The solver dynamically adjusts the vehicular glide schedule in response to a change in one of the at least one data set.

Abstract: A technique for managing data processed by multiple processing engines comprises storing a first data block associated with a first processing engine in a first portion of a ring buffer memory, subsequent to storing the first data block, storing a second data block associated with a second processing engine in a second portion of the ring buffer memory, and receiving a second process complete signal from the second processing engine while waiting for a first process complete signal from the first processing engine. The technique further comprises receiving the first process complete signal from the first processing engine once the first processing engine completes processing of the first data block, and, upon receiving the first process complete signal, indicating that the first portion of the ring buffer memory is available for storing data other than the first data block.

Abstract: A decode engine is configured to perform a rotation operation with a macroblock in conjunction with performing a deblocking operation that involves the macroblock. The decode engine decodes the macroblock and performs the deblocking operation to generate a deblocked macroblock, then rotates the deblocked macroblock and writes the rotated, deblocked macroblock to memory. With this approach, multiple, redundant reads of the macroblock, as required with conventional rotation techniques, may be avoided.