Patents by Inventor Richard Gavin Bramley

Richard Gavin Bramley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11720472
    Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: August 8, 2023
    Assignee: NVIDIA Corporation
    Inventors: Richard Gavin Bramley, Philip Payman Shirvani, Nirmal R. Saxena
  • Publication number: 20220114075
    Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.
    Type: Application
    Filed: November 9, 2021
    Publication date: April 14, 2022
    Inventors: Richard Gavin Bramley, Philip Payman Shirvani, Nirmal R. Saxena
  • Patent number: 11188442
    Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: November 30, 2021
    Assignee: NVIDIA Corporation
    Inventors: Richard Gavin Bramley, Philip Payman Shirvani, Nirmal R. Saxena
  • Publication number: 20200293425
    Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. In some cases, memory faults can be diagnosed by redundant execution and a diagnostic coverage may be determined.
    Type: Application
    Filed: April 15, 2020
    Publication date: September 17, 2020
    Inventors: Richard Gavin Bramley, Philip Payman Shirvani, Nirmal R. Saxena
  • Patent number: 10691572
    Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. A method, computer readable medium, and system are provided for using liveness as a factor to evaluate memory vulnerability to soft errors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 23, 2020
    Assignee: NVIDIA Corporation
    Inventors: Richard Gavin Bramley, Philip Payman Shirvani, Nirmal R. Saxena
  • Publication number: 20190065338
    Abstract: Memory, used by a computer to store data, is generally prone to faults, including permanent faults (i.e. relating to a lifetime of the memory hardware), and also transient faults (i.e. relating to some external cause) which are otherwise known as soft errors. Since soft errors can change the state of the data in the memory and thus cause errors in applications reading and processing the data, there is a desire to characterize the degree of vulnerability of the memory to soft errors. In particular, once the vulnerability for a particular memory to soft errors has been characterized, cost/reliability trade-offs can be determined, or soft error detection mechanisms (e.g. parity) may be selectively employed for the memory. A method, computer readable medium, and system are provided for using liveness as a factor to evaluate memory vulnerability to soft errors.
    Type: Application
    Filed: August 28, 2018
    Publication date: February 28, 2019
    Inventors: Richard Gavin Bramley, Philip Payman Shirvani, Nirmal R. Saxena
  • Patent number: 10216521
    Abstract: A method, computer readable medium, and system are disclosed for error coping. The method includes the steps of receiving, by a processing unit, a set of program instructions including a first program instruction that is responsive to error detection, detecting an error in a value of a first operand of the first program instruction, and determining that error coping execution is selectively enabled for the first instruction. The value for the first operand is replaced with a substitute value and the first program instruction is executed by the processing unit.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 26, 2019
    Assignee: NVIDIA Corporation
    Inventors: Philip Payman Shirvani, Richard Gavin Bramley, John Montrym
  • Publication number: 20180365017
    Abstract: A method, computer readable medium, and system are disclosed for error coping. The method includes the steps of receiving, by a processing unit, a set of program instructions including a first program instruction that is responsive to error detection, detecting an error in a value of a first operand of the first program instruction, and determining that error coping execution is selectively enabled for the first instruction. The value for the first operand is replaced with a substitute value and the first program instruction is executed by the processing unit.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Philip Payman Shirvani, Richard Gavin Bramley, John Montrym