Patents by Inventor Richard Gene Burch

Richard Gene Burch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6317640
    Abstract: Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: November 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Suraj Rao, Sharad Saxena, Pushkar P. Apte, Purnendu K. Mozumder, Richard Gene Burch, Karthik Vasanth, Joseph Carl Davis, Chenjing L. Fernando
  • Patent number: 5901062
    Abstract: A semiconductor structure design and process visualization tool (10). A main menu (30) allows a user to add, edit or delete process steps (16a-f) to create a process flow in process flow window (12). Main menu (30) provides a set of process models to be selected from. The set of process models are simple first-order geometric models that require only physical parameters of a resulting device layer. Specific process conditions are not required. Semiconductor process and wafer representation tool applies the physical parameters to the corresponding process model to quickly create a cross-section (20) in cross-section window (22) corresponding to a selected process step (16d) in process flow window (12).
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: May 4, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Richard Gene Burch, Purnendu Kanti Mozumder