Patents by Inventor Richard Grenier

Richard Grenier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10888741
    Abstract: The present invention generally relates to lightweight, portable robot for analyzing golf balls for short game performance attributes. The preferred robot is specifically designed to be lightweight and portable and to be able to hit a golf ball off of the ground or a mat that simulates the ground such that realistic short game performance of clubs and balls can be evaluated.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 12, 2021
    Assignee: Acushnet Company
    Inventors: Michael J. Toupin, Paul A. Furze, Richard Daprato, Glenn Grenier, Anthony J. Couto, William Souza
  • Patent number: 10802723
    Abstract: Embodiments of the present invention provide tightly coupled off-die memory along with an interface bus and smart buffer logic so as to efficiently perform certain frequent or repetitive operations off of a core logic. Embodiments of the present invention relieve the core logic from performing certain repetitive or frequent memory accesses and other operations so as to allow such core logic to perform other more general or varied operations. In this way, the universal interface bus, smart buffer logic, and off-die memory are specially configured to perform certain select frequent and repetitive operations while the core logic may configured to perform other operations so as to provide an improved configuration with increased computational capability and reduced power budget.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 13, 2020
    Assignee: Altera Corporation
    Inventors: Richard Grenier, Arif Rahman
  • Patent number: 9983990
    Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, a processing circuit, and a configurable control circuit. The configurable storage block may receive an instruction which may be decoded in the control block to identify a command. The command may be associated with a pre-defined sequence of operations that the control block executes by directing the memory array to perform memory access operations and the processing circuit to execute data processing operations. These data processing operations may be executed on data retrieved during memory access operations, data received subsequent to receiving the instruction, or previously computed data. The processed data may be provided for further processing outside the configurable storage block or stored in the memory array. The configurable storage block may further have delay blocks to allow for delayed memory access to the memory array.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: May 29, 2018
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Richard Grenier
  • Publication number: 20160358653
    Abstract: An integrated circuit die having hardware processing elements with a configurable embedded search engine for a content addressable memory is disclosed. The circuit die includes an area having hardware processor circuits. A search engine is coupled to the circuit die via an interconnection. The search engine receives requests for data content. A content addressable memory is coupled to the search engine. The content addressable memory is searchable by the search engine in response to a search request from the hardware processor circuit for data content.
    Type: Application
    Filed: June 8, 2015
    Publication date: December 8, 2016
    Inventors: Richard Grenier, Anargyros Krikelis
  • Patent number: 9338100
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 10, 2016
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
  • Publication number: 20140153389
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Application
    Filed: June 24, 2013
    Publication date: June 5, 2014
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
  • Patent number: 8493988
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 23, 2013
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
  • Publication number: 20110110237
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Application
    Filed: September 13, 2010
    Publication date: May 12, 2011
    Applicant: Foundry Networks, LLC
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
  • Patent number: 7817659
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: October 19, 2010
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier
  • Publication number: 20090279559
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Application
    Filed: March 26, 2004
    Publication date: November 12, 2009
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier