Abstract: A system for integrated cargo inspection includes a non-invasive imaging system scanning a cargo container during an offload operation to obtain a digital image of its contents, a server including a control processor to control components of the system. The components including a computer vision system to perform vision system recognition techniques on the digital image and prepare a report having image icons representing the contents, a machine learning system analytically reviewing the report to generate heuristic analysis used to train the vision system, a computing device displaying at least one of a port plan, a scan view, a results list form dialog, and a results history log graphical displays. A method to implement the system and a non-transitory computer-readable medium are also disclosed.

Abstract: A radar system to track objects for a vehicle may include a plurality of transmitters to transmit a signal; a plurality of receivers to receive the signal; and an adjustment circuit to adjust the bandwidth of the transmitted signal in accordance with the received signal from the receivers of the radar system.

Abstract: The present invention includes an artificial intelligence system for acquiring real-time positioning and geographic data and generates a control signal received by a digital beam forming and steering system for adaptive detection, ranging, and tracking of moving objects for example vehicles. This system is particularly effective in detecting and tracking moving vehicles, obstacles and pedestrians on curved roads and blind spots behind corners of roads.

Abstract: A system for integrated cargo inspection includes a non-invasive imaging system scanning a cargo container during an offload operation to obtain a digital image of its contents, a server including a control processor to control components of the system. The components including a computer vision system to perform vision system recognition techniques on the digital image and prepare a report having image icons representing the contents, a machine learning system analytically reviewing the report to generate heuristic analysis used to train the vision system, a computing device displaying at least one of a port plan, a scan view, a results list form dialog, and a results history log graphical displays. A method to implement the system and a non-transitory computer-readable medium are also disclosed.

Abstract: A master voltage controlled oscillator (VCO) produces an output signal at an operating frequency of at least 100 gigaHertz (GHz). A buffer VCO injection-locked to an output of the master VCO produces an output signal at the operating frequency with a voltage swing greater than 50% of an output voltage swing of the master VCO output signal. The buffer VCO operates without pulling, and can drive a load of at least three times greater than a nominal load. Phase noise in the output of the buffer VCO is as much as ?96 decibels (dB) relative to the carrier (dBc) per Hertz (Hz) at 125 GHz with a 1 megaHertz (MHz) offset.

Abstract: A master voltage controlled oscillator (VCO) produces an output signal at an operating frequency of at least 100 gigaHertz (GHz). A buffer VCO injection-locked to an output of the master VCO produces an output signal at the operating frequency with a voltage swing greater than 50% of an output voltage swing of the master VCO output signal. The buffer VCO operates without pulling, and can drive a load of at least three times greater than a nominal load. Phase noise in the output of the buffer VCO is as much as ?96 decibels (dB) relative to the carrier (dBc) per Hertz (Hz) at 125 GHz with a 1 megaHertz (MHz) offset.

Abstract: The present disclosure describes methods, systems, and computer program products for providing enhanced business consolidation system reporting functionality according to an implementation.

Abstract: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Abstract: There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. Here, however, a single stage divider has been provided that is adapted to operate at very high frequencies (i.e., 120 GHz). To accomplish this, it uses parasitic capacitances in conjunction with inductor(s) to form an LC tanks so as to take advantages of parasitics that normal degrade performance.

Abstract: Traditionally, low-noise amplifiers or LNAs have been used in high frequency applications, but for very high frequency ranges (i.e., 60 GHz), building an LNA to meet performance needs has been difficult. Here, however, an LNA has been provided that operates well around 60 GHz. In particularly, this LNA is generally unconditionally stable, has a generally low noise factor or NF, and has a generally high gain around 60 GHz.

Abstract: There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. Here, however, a single stage divider has been provided that is adapted to operate at very high frequencies (i.e., 120 GHz). To accomplish this, it uses parasitic capacitances in conjunction with inductor(s) to form an LC tanks so as to take advantages of parasitics that normal degrade performance.

Abstract: Traditionally, low-noise amplifiers or LNAs have been used in high frequency applications, but for very high frequency ranges (i.e., 60 GHz), building an LNA to meet performance needs has been difficult. Here, however, an LNA has been provided that operates well around 60 GHz. In particularly, this LNA is generally unconditionally stable, has a generally low noise factor or NF, and has a generally high gain around 60 GHz.

Abstract: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Abstract: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Abstract: The charge pump circuit includes: a charge pump output branch having a first transistor and a second transistor coupled in series; an output branch replica having a third transistor and a fourth transistor coupled in series; a feedback circuit coupled between the output branch and the output branch replica; a charge pump input circuit coupled to the charge pump output branch, and having first and second input branches; and an input circuit branch replica controlled by the feedback circuit and coupled to the charge pump input circuit.

Abstract: The charge pump circuit includes: a charge pump output branch having a first transistor and a second transistor coupled in series; an output branch replica having a third transistor and a fourth transistor coupled in series; a feedback circuit coupled between the output branch and the output branch replica; a charge pump input circuit coupled to the charge pump output branch, and having first and second input branches; and an input circuit branch replica controlled by the feedback circuit and coupled to the charge pump input circuit.

Abstract: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Abstract: An array update operation which specifies number of (row-identifier, value) pairs for updating rows in a table of a database is implemented as follows. A block-identifier of a block (on disk) that holds a row identified by a row-identifier in a specified pair is looked up using a database index, and the block-identifier thus found is stored in a structure. Use of a row-identifier to look up the corresponding block-identifier, and the storage of the block-identifier in the structure are repeatedly performed, for each of several specified pairs. Next, a vector read is performed, to read and store in a cache, each block identified by a block-identifier in the structure, and all the blocks that have been read are stored in the cache during a single function call. Thereafter, rows identified in specified pairs are modified, in blocks currently in the cache, using the values in the specified pairs.

Abstract: An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Abstract: A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed loop comprises both a phase locked loop (PLL) and a delay locked loop (DLL) in a novel time division multiplex data recovery system. This new architecture comprises a 4 stage Voltage Controlled Oscillator (VCO) used to generate 8 clock signals, 45 degrees phase shifted from one another, for 8 receivers to do the oversampling. An interpolator tracks the received data signal and feeds it back to the Phase/Frequency Detector (PFD). The PFD has a second input of the reference clock which the PFD uses along with the interpolator input to correct the frequency of the PLL. The PLL operates at a high bandwidth. The DLL's bandwidth is several orders lower than the PLL. The DLL activates only a multiplexer and an interpolator continuously, thereby drawing a minimum amount of power.