Abstract: Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and automated sequencing through multiple pages of the stored script or score. The performer can modify timing of sequencing if desired, for example dependent on performance speed or musical complexity. Automated highlighting or marking of measures or text assists the performer in keeping track of progress through the performance. During or after the performance, electronic comparison of the performance to the score or script provides feedback to the performer, highlighting differences between the actual performance and the desired performance as described by the score or script.

Abstract: Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and automated sequencing through multiple pages of the stored script or score. The performer can modify timing of sequencing if desired, for example dependent on performance speed or musical complexity. Automated highlighting or marking of measures or text assists the performer in keeping track of progress through the performance. During or after the performance, electronic comparison of the performance to the score or script provides feedback to the performer, highlighting differences between the actual performance and the desired performance as described by the score or script.

Abstract: The invention provides a method of fabricating a semiconductive device [200]. In this embodiment, the method comprises depositing a hydrocarbon layer [294] over a semiconductive substrate, forming an interconnect structure [295, 297] within the hydrocarbon layer [294], and removing the hydrocarbon layer [294] by sublimation.

Abstract: A system and methods are described for the evaluation of the integrity of a wafer cassette and the disposition thereof based upon evaluation of wafer measurement data obtained using a wafer sorter cassette mapping system utilized in-line during wafer sorting operations. One method comprises initially placing two or more wafers into two or more of a plurality of slots in the wafer cassette. A wafer sorter cassette mapping sensor affixed to the wafer sorter is then scanned over the two or more wafers in the slots of the wafer cassette, using a wafer sorter. The positions of the wafers in the wafer cassette are then measured while scanning the sensor over the wafers. The wafer position measurements are then evaluated using a modeling system to determine slot positions within the cassette associated with the wafer position measurements, and a determination of the integrity of the cassette is generated based on the slot position determinations.

Abstract: Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.

Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer. The wafer includes an array of die that includes a plurality of complete die and at least one partial edge die. The wafer has an edge that has a substantially rounded profile causing undersized patterns in semiconductor devices formed on partial edge die. A first exposure intensity is assigned to a first group of die on the surface of the wafer. The first group of die includes a group of complete die, and the first exposure intensity is assigned based at least in part on the location of the first group of die on the surface of the wafer. A second exposure intensity is assigned to a second group of die on the surface of the wafer. The second group of die includes at least one partial edge die. The second exposure intensity less than the first exposure intensity to compensate for reduced line width due to the wafer edge topography.

Abstract: A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

Abstract: The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other steps, placing a substrate 290 in an enclosure 200 being substantially devoid of unwanted contaminants and forming a material layer 310 over the substrate 290 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants. The electroplating process further includes forming a thin layer of oxide 410 over the material layer 310 within the enclosure 200, the enclosure 200 still being substantially devoid of the unwanted contaminants during the forming the thin layer of oxide 410.

Abstract: The present invention provides a system for removing surface contaminants from a copper seed layer disposed upon a semiconductor substrate (210), in preparation for electrochemical deposition. An electrochemical deposition apparatus (202) is provided, having a contaminant remediation module (204) housed within. The semiconductor substrate (210) is transferred into the remediation module (204), where it is exposed in a reactive remediation system (216). Contaminants are removed from the surface of the copper seed layer, followed by an immediate transfer (212) of the substrate (210) from the remediation module (204) into a plating system (208) also housed within the electrochemical deposition apparatus (202).