Abstract: A dual port memory has been provided which allows read and write operations by separate data processors during a read cycle of one of the processors. A method of accomplishing this is provided by shortening the column drive signal to disconnect the column line from the sense amplifier once the sense amplifier has latched the data being read. Write circuitry can then be enabled to write into the memory cell which has just been read by the sense amplifier.

Abstract: A reference voltage generator useful in a memory having memory locations capable of storing more than two states provides references which are used to determine which state is stored in a selected memory cell. The output of the reference voltage generator is connected to comparator circuitry which also receives the output from the selected memory cell. The reference voltage generator generates each one of the required voltages every time a row is selected in the memory. The comparator circuitry serves as a sense amplifier and provides a memory output.

Abstract: A memory system having a plurality of memory cells each capable of storing more than two states also has a reference voltage generator which is used to determine the state stored in a selected memory cell. The plurality of memory cells are arranged in groups of columns, and in a preferred embodiment, the reference voltage generator is arranged in columns which are located between two of the groups of columns. The memory system uses voltage sensing as opposed to current sensing and therefore the only current used is to charge line capacitances. The voltage reference generator is only enabled during the period of time that a cell is being read from.

Abstract: A level shifter using complementary metal oxide semiconductor (CMOS) transistors is provided. A first transistor couples a first voltage to a node of the level shifter circuit, and the first transistor is controlled by an input signal. A P-channel and an N-channel MOS device are connected in series between the first voltage and a second voltage. The gate electrodes of the P-channel and N-channel MOS devices are connected to the node. An output for the level shifter circuit is taken from a junction formed by the P-channel and N-channel MOS devices. A resistance is coupled between the gate electrodes of the P-channel and the N-channel MOS devices and the second voltage.