Abstract: A method of manufacturing a device in a wafer with a P-type semiconductor, includes forming on a surface of the semiconductor body a layer of silicon dioxide doped with an N-type dopant. The portion of the doped silicon dioxide covering the interconnect work site area is removed and a masking layer of an oxidation impervious medium is formed over the wafer and thereafter removed from the field areas, as is the doped silicon dioxide layer. A thin layer of gate oxide is formed over the field areas. A layer of conductive polysilicon is formed over the entire wafer followed by a layer of oxygen impervious masking medium. The conductive polysilicon and masking medium layers are removed from all areas of the wafer except those whereat transistors are to be formed. The wafer is exposed to an oxidizing environment under an elevated temperature producing a field oxide over the exposed gate oxide.

Abstract: A shift register is described particularly adapted for selectively controlling the energization of the windings of a stepping motor so as to provide selective overlapping phase energization. The shift register consists of four stages each having master and slave sections with each stage controlling the energization of an associated motor winding. A shift register control unit, responsive to stepping and directional signals, directs the shifting of information between the various stages of the shift register. In response to a step high input signal, a high level of one shift register stage is shifted in a selected direction to the adjacent stage with both stages directing the energization of their respective motor windings. Similarly, in response to a step low signal the low levels of the shift register stages are shifted in a selected direction to their adjacent stages causing the deenergization of the respective motor windings.

Abstract: A method of manufacturing devices in a semiconductor body 20 of a first conductivity type. An oxygen impervious masking medium 22 is placed on the body 20. Portions of the medium 22 are removed to define field areas 31 and field oxide is formed in the field areas. The surface of the silicon wafer 23 is thereafter masked to define gate areas 26 and electrical contact areas 30. The exposed medium is removed and the exposed body areas doped to form interconnect runs 28 and a source/drain region 29 of a second conductivity type. An oxide 48, 50 is formed over the doped interconnect runs and source/drain regions of the wafer. The masking medium covering the contact area 30 is removed and the contact area is doped to a second conductivity type. Finally conductors 60, 61 are positioned to provide the desired electrical connections.

Abstract: Portions of a doped silicon body 22 are covered with an oxide dielectric 26 leaving the active areas 25 on the silicon body exposed. A polysilicon layer 28 having a predetermined resistance characteristic is formed over the entire wafer surface followed by a layer of silicon nitride 30. Selected portions of the silicon nitride layer 30 are removed with the nitride remaining over the source/drain regions 36 of the active area and the locations of first level conductor runs 32. The exposed polysilicon 28 is converted to an oxide and the silicon nitride 30, covering the source/drain regions 36 and the first level conductor runs, is removed. The exposed polysilicon is doped forming source/drain diffusions 46 and first level conductors 32. An oxide dielectric 52 is formed over the wafer 20 and removed from the gate areas 56 followed by the formation of a thin gate dielectric 54. Finally the oxide 52 is removed at the interconnect work sites and second level conductors 58, 60 are formed.

Abstract: A silicon body (10) of a first conductivity type is covered with a sandwich of silicon dioxide (12), polycrystalline silicon (14) and silicon nitride (16). Source, drain, and interconnect work sites of the body are exposed by a first photoshaping operation. The work sites are doped forming regions (21, 22, 23) of a second conductivity type. Silicon dioxide (24, 26, 28) is grown over the work sites. A second photoshaping operation provides an opening 36. The walls of the opening 36 on two opposite sides comprise sides of the sandwich layer as established by the first photoshaping operation and the two remaining walls comprise sides of the silicon dioxide as established by the second photoshaping operation. Silicon nitride (44) is next deposited over the entire wafer (15) which is then photoshaped to define the field regions (46, 48). The etching process is continued to remove part of the silicon body as well as the sides of those exposed regions.

Abstract: A shift register is described particularly adapted for selectively controlling the energization of the windings of a stepping motor so as to provide selective overlapping phase energization. The shift register consists of four stages each having master and slave sections with each stage controlling the energization of an associated motor winding. A shift register control unit, responsive to stepping and directional signals, directs the shifting of information between the various stages of the shift register. In response to a step high input signal, a high level of one shift register stage is shifted in a selected direction to the adjacent stage with both stages directing the energization of their respective motor windings. Similarly, in response to a step low signal the low levels of the shift register stages are shifted in a selected direction to their adjacent stages causing the deenergization of the respective motor windings.

Abstract: An integrated circuit Read-Only Memory (ROM) with improved speed of operation is disclosed as generally representative of similarly improved logic arrays. The ROM includes parallel rows of conductors oriented normal to parallel doped regions which form column conductors. The ROM is implemented with field-effect transistors and comprises two decoder fields and a data field. The transistors of the decoder fields serve to define open circuits between adjacent column conductors in accordance with binary input signals applied to the decoder fields. In the illustrative ROM, a first column conductor is connected to a return terminal of a power supply and a second column conductor is connected to a "pull-up" circuit. The illustrative circuit provides for the connection of power supply return connections to both ends of the one column conductor and provides for the connection of pull-up circuits to both ends of the second column conductor.

Abstract: A circuit is described for controlling a programmable logic array adapted for use with a communications terminal. The logic array includes an input AND-section defined by a plurality of addressable fields and an output OR-section. One field of the input section is addressed by an incoming address register selectively loaded with incoming data. A second field is addressed by a branch address register loaded with selective outputs of the output section thus providing program branching capabilities. Also, a loop counter and a clocked program counter address two additional fields of the input section. The loop counter facilitates program looping in the logic array while the program counter affords real time operational characteristics for the control circuit.

Abstract: A dynamic logic system is disclosed in which a capacitor is charged by a clock signal through a gating device. The capacitor is either discharged or remains at its charged value in response to the impedance of a logic circuit. Two such systems are disclosed in which the output from the first logic system is applied as an input to the second logic system.

Abstract: A phased, four-output clock generator implemented on-chip with MOSFETs, has two phased inputs .phi..sub.A and .phi..sub.B thereto. If .phi..sub.A and .phi..sub.B are properly time-phased (in sequence: .phi..sub.A =1, .phi..sub.B =0; .phi..sub.A =0, .phi..sub.B =0; .phi..sub.A =0, .phi..sub.B =1; and .phi..sub.A =0, .phi..sub.B =0) the four outputs are time phased as:______________________________________ .phi..sub.1 .phi..sub.2 .phi..sub.3 .phi..sub.4 ______________________________________ t.sub.1 1 0 0 0 t.sub.2 0 1 0 0 t.sub.3 0 0 1 0 t.sub.4 0 0 0 1 ______________________________________The clock includes two timers each of which contains a phasing module and a NOR-gate. The phasing modules have two inputs A and B and produce an output as follows: ______________________________________ A B Output ______________________________________ 0 0 P 0 1 0 1 0 1 1 1 0 ______________________________________where "P" indicates that the last succeeding output is left unchanged or stretched.

Abstract: A read-only memory and sense amplifier system for sensing whether a selected memory cell of a memory bank includes a high-impedance memory device, or a low-impedance device, and for generating a binary output signal representing stored data in response to the sensed difference. The cells are programmed with a pattern of high and low-impedance devices, such as inoperative and operative field-effect transistors in accordance with stored data. The memory bank, including the impedance of the selected cell, is connected to a first input node of the amplifier, and has either: (A) a first or "ON" bank impedance between the first node and a reference node, such as circuit ground, if the selected cell is in the low-impedance state: or (B) a second or "OFF" bank impedance if the selected cell is in the high-impedance state. A reference impedance is connected between the other amplifier node and the reference node, and has a value between the ON bank impedance and the OFF bank impedance.

Abstract: In one example, a generally conventional flip-flop circuit is used, including a pair of input field-effect transistors having their gates connected respectively to a pair of circuit nodes A and B. During a preset portion of the cycle, both nodes A and B are preset to an initial reference potential V.sub.R, set so that the transistors turn partially ON and act as variable resistors. Thereafter, an unknown voltage V.sub.X to be sensed is connected to node A, V.sub.X being equal to V.sub.R .+-. .DELTA.V. The flip flop then responds to differential conductivity between the transistors, to produce a binary output voltage at one of two levels set by the sense of .DELTA.V, plus or minus.In a semiconductor RAM circuit, selected memory cell capacitors are connected in sequence to node A, and the flip-flop circuit senses the cell charge and produces an amplified output representative thereof, which is later fed back to the memory cell to refresh the charge originally stored therein.

Abstract: A static logic circuit utilizing transistors of the MOSFET type includes a high resistance load transistor, a low resistance logic network having a large self-loading capacitance, and a gating transistor connected in series between the network and the load device. The logic network controls the output voltage across a load capacitor by grounding the load transistor output for selected input data, and the gating transistor is biased to turn OFF when the voltage across the large self-loading capacitance exceeds a predetermined level, thereafter isolating the input network from the load capacitor and speeding up the output transition by decreasing the time required to charge the load capacitor.

Abstract: A gate circuit includes field effect transistors interconnected to provide an output signal of a first type whenever all input signals are of predetermined types, and to provide an output of a second type whenever any input signal is other than one of the predetermined types, wherein the only current required by the circuit is that supplied by the output of the circuit to a load which is driven by the circuit. Preferably, the circuit includes a plurality of logic-steering field effect transistors connected with their controlled electrodes in series such that an input signal is connected to an output load device, such as a capacitor, only if all of the logic-steering transistors have been turned ON. A ground return transistor is provided for each logic-steering transistor and operates to provide a ground at the output of the logic-steering transistor if an improper input signal is received.