Abstract: Solid state switches of inverters are controlled by timing signals computed in power layer interface circuitry for individual inverters. Multiple inverters may be placed in parallel with common three-phase output. Common control circuitry generates timing signals or data used to reconstruct the common signals and sends these signals to the power layer interface circuitry. A processor in a power layer interface circuitry used these signals to recomputed the timing signals. Excellent synchronicity may be provided between parallel inverters that each separately reconstruct the timing signals based upon the identical received data.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: A technique is provided for verifying the proper selection, installation, communication and operability of components in power electronic systems, such as motor drives. A processing circuit is coupled to multiple components or subsystems that identify themselves to the processing system. An identification code is stored that is compared to a similar code built based upon the information reported by the components at the time of commissioning, operation or servicing. If the comparison indicates that all components are properly installed, and communicating and operative, operation may continue. The technique may be applied in parallel motor drives at a power layer level to allow separate and parallel verification of component and component operation in the parallel drives.

Abstract: Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry.

Abstract: Solid state switches of inverters are controlled by timing signals computed in power layer interface circuitry for individual inverters. Multiple inverters may be placed in parallel with common three-phase output. Common control circuitry generates timing signals or data used to reconstruct the common signals and sends these signals to the power layer interface circuitry. A processor in a power layer interface circuitry used these signals to recomputed the timing signals. Excellent synchronicity may be provided between parallel inverters that each separately reconstruct the timing signals based upon the identical received data.

Abstract: Solid state switches of inverters are controlled by timing signals computed in power layer interface circuitry for individual inverters. Multiple inverters may be placed in parallel with common three-phase output. Common control circuitry generates timing signals or data used to reconstruct the common signals and sends these signals to the power layer interface circuitry. A processor in a power layer interface circuitry used these signals to recomputed the timing signals. Excellent synchronicity may be provided between parallel inverters that each separately reconstruct the timing signals based upon the identical received data.

Abstract: Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry.

Abstract: A technique is provided for verifying the proper selection, installation, communication and operability of components in power electronic systems, such as motor drives. A processing circuit is coupled to multiple components or subsystems that identify themselves to the processing system. An identification code is stored that is compared to a similar code built based upon the information reported by the components at the time of commissioning, operation or servicing. If the comparison indicates that all components are properly installed, and communicating and operative, operation may continue. The technique may be applied in parallel motor drives at a power layer level to allow separate and parallel verification of component and component operation in the parallel drives.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: Solid state switches of inverters are controlled by timing signals computed in power layer interface circuitry for individual inverters. Multiple inverters may be placed in parallel with common three-phase output. Common control circuitry generates timing signals or data used to reconstruct the common signals and sends these signals to the power layer interface circuitry. A processor in a power layer interface circuitry used these signals to recomputed the timing signals. Excellent synchronicity may be provided between parallel inverters that each separately reconstruct the timing signals based upon the identical received data.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry.

Abstract: A technique is provided for verifying the proper selection, installation, communication and operability of components in power electronic systems, such as motor drives. A processing circuit is coupled to multiple components or subsystems that identify themselves to the processing system. An identification code is stored that is compared to a similar code built based upon the information reported by the components at the time of commissioning, operation or servicing. If the comparison indicates that all components are properly installed, and communicating and operative, operation may continue. The technique may be applied in parallel motor drives at a power layer level to allow separate and parallel verification of component and component operation in the parallel drives.

Abstract: A system and method for controlling an inverter of a motor control unit includes a controller having a user interface configured to allow user selection of a waveform increment value or a waveform amplitude threshold. The controller also includes an integrator configured to receive the waveform increment value and generate a signal at least based on the waveform increment value. A logic circuit is configured to monitor the signal and reset the integrator when the signal reaches the waveform amplitude threshold to generate a waveform having a frequency-independent amplitude. A comparator compares the waveform to a modulating signal to trigger gating pulses delivered to an inverter to drive an associated motor.

Abstract: A system and method for controlling an inverter of a motor control unit includes a controller having a user interface configured to allow user selection of a waveform increment value or a waveform amplitude threshold. The controller also includes an integrator configured to receive the waveform increment value and generate a signal at least based on the waveform increment value. A logic circuit is configured to monitor the signal and reset the integrator when the signal reaches the waveform amplitude threshold to generate a waveform having a frequency-independent amplitude. A comparator compares the waveform to a modulating signal to trigger gating pulses delivered to an inverter to drive an associated motor.