Patents by Inventor Richard H. Shanaman, III

Richard H. Shanaman, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5366924
    Abstract: A process for planarizing a bonded wafer. The wafer has a layer of exposed oxide thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer for subsequent fabrication of transistors, etc.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: November 22, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: William G. Easter, Richard H. Shanaman, III
  • Patent number: H1137
    Abstract: A process for forming a dielectrically isolated wafer is disclosed. In particular, the conventional process is altered to replace the step of growing the thick polysilicon handle layer with the steps of growing a relatively thin conformal coating layer and bonding a single crystal wafer thereto. The wafer will become the substrate of the final device structure. The process of bonding is considered to be more efficient and economical than the prior art polysilicon growth process. Additionally, the tub structures of the wafer bonding process may be exposed to a somewhat lower temperature (for bonding) for shorter period of time than the tub regions of the conventional thick polysilicon DI structures. Therefore, the tub regions will exhibit superior qualities (e.g., less stress, fewer crystal defects) when compared with those formed with the conventional polysilicon growth technique.
    Type: Grant
    Filed: November 5, 1990
    Date of Patent: February 2, 1993
    Assignee: American Telephone and Telegraph Company
    Inventors: William G. Easter, Richard H. Shanaman, III
  • Patent number: H1174
    Abstract: A process for forming a dielectrically isolated wafer is disclosed. In particular, the conventional process is altered to replace the step of growing the thick polysilicon handle layer with the steps of growing a relatively thin conformal coating layer and bonding a single crystal wafer thereto. The wafer will become the substrate of the final device structure. The process of bonding is considered to be more efficient and economical than the prior art polysilicon growth process. Additionally, the tub structures of the wafer bonding process may be exposed to a somewhat lower temperature (for bonding) for shorter period of time than the tub regions of the conventional thick polysilicon DI structures. Therefore, the tub regions will exhibit superior qualities (e.g., less stress, fewer crystal defects) when compared with those formed with the conventional polysilicon growth technique.
    Type: Grant
    Filed: August 7, 1991
    Date of Patent: April 6, 1993
    Assignee: American Telephone and Telegraph Company
    Inventors: William G. Easter, Richard H. Shanaman, III