Abstract: A method for controlling wear level operations in solid state memory. The method includes receiving a request to write to a memory location identified by a write address of the solid state memory, and making a first determination that the writing to the memory location results in a duplicate write to the memory location. The method further includes, based on the first determination, making a second determination that a number of encountered duplicate writes has reached an adaptively controlled maximum number of duplicate writes, and based on the second determination, performing a wear level operation.

Abstract: Logical to physical mapping of managed units (“MUs”) of object data in a flash memory system storing MUs that are being created continuously by applications running on a client system is maintained in an extent based tree in DRAM for extents of contiguous MUs and in an override tree in DRAM for individual MUs. Extent mapping data in the extent tree for extents comprises a starting address and a length. Mapping data for individual MUs in the override tree comprises individual pointers from logical addresses to physical addresses. Source erase blocks in flash memory are reorganized asynchronously by iteratively moving individual MUs of an object in order from a source erase block to a free erase block to empty the source erase block and free up associated DRAM.

Abstract: In general, embodiments of the technology relate to a method for storing data. The method includes receiving a request to write data. In response to the request, the method further includes, selecting a first physical address in a first region in a first storage module, selecting a second physical address in a second region in a second storage module, where an amount of wear associated with the first physical address is different than an amount of wear associated with the second physical address, writing a first copy of the data to the first physical address, and writing a second copy of the data to the second physical address.

Abstract: A method for mitigating the effect of write disturbances in solid state memory. The method includes receiving a request to write to a memory location of the solid state memory, writing to the memory location, identifying a disturbed memory location, identifying a memory region that includes the disturbed memory location, identifying an address, in the memory region, of the disturbed memory location, generating an address hash from the address, and making a first determination that a history of disturbed memory locations in the memory region includes the address hash. The method further includes, based on the first determination, clearing the history of disturbed memory locations, making a second determination that a wear level operation is due, and based on the second determination, performing the wear level operation.

Abstract: A method for recovering storage object records in solid state memory. The method includes, for each memory location of a solid state memory region, reading data fragment metadata and identifying, based on the data fragment metadata, a storage object. The storage object occupies a subset of memory locations of the memory locations of the solid state memory region. The method further includes identifying a first and a last memory location of the subset of memory locations, and restoring a storage object record for the storage object, wherein the storage object record comprises variables that enable a logical to physical address translation for the storage object.

Abstract: A method for dynamic write-back cache sizing in solid state memory storage. The method includes receiving a request to write a data fragment to a memory location of a storage medium, identifying a resource required for the writing, and obtaining a state of the resource. The state of the resource is governed by a number of data fragments that are stored in the write-back cache which require the resource. The number of data fragments in the write-back cache which require the resource are limited to enable writing of all data fragments in the write-back cache to the storage medium, within a specified amount of time. The method further includes determining that the state of the resource allows the received data fragment to be stored in the write-back cache, and based on the determination: storing the data fragment in the write-back cache and acknowledging the write request.

Abstract: A data storage device includes a persistent storage and a processor. The persistent storage stores data. The processor obtains a data access request for the data stored in the persistent storage, obtains a portion of the data from the persistent storage using a global migration progress index, and provides the obtained portion of the data in response to the data access request.

Abstract: In general, embodiments of the technology relate to a method for storing data. The method includes receiving a request to write data. In response to the request, the method further includes, selecting a first physical address in a first region in a first storage module, selecting a second physical address in a second region in a second storage module, where an amount of wear associated with the first physical address is different than an amount of wear associated with the second physical address, writing a first copy of the data to the first physical address, and writing a second copy of the data to the second physical address.

Abstract: A method for data migration in solid state memory. The method includes making a first determination that a write limit of a first memory region of the solid state memory has been reached, and based on the first determination: allocating a second memory region in the solid state memory. The method further includes, based on making the first determination: migrating a first data fragment from a first memory location in the first memory region to a corresponding second memory location in the second memory region, updating a migration progress index to include the second memory location, directing future read and write requests that target memory locations included in the migration progress index to the second memory region, and directing future read and write requests that target memory locations not included in the migration progress index to the first memory region.

Abstract: A request is received via a message submission queue. The request is sent from a core associated with an external processor coupled by a communication interface. The message submission queue is associated with a memory access engine circuit configured to perform one or more memory access functions. The memory access engine circuit is used to dequeuer a next message from its corresponding message submission queue. The memory access engine circuit is used to perform a message function invoked by the message. The memory access engine circuit is used to receive a result of performing the message function. The memory access engine circuit is used to prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.

Abstract: A non-volatile memory has multi-level arrays of write-in place memory cells that are subject to change over time because of read and write disturbs. Disturb count counters of each read cell and each cell surrounding a written target cell are incremented by different scaling factors that reflect the effect of the disturbs on each such cell. Upon a counter reaching a predetermined threshold, a refresh of the cell is initiated.

Abstract: A method for controlling wear level operations in solid state memory. The method includes receiving a request to write to a memory location identified by a write address of the solid state memory, generating a write address hash from the write address, making a first determination that a write history for a memory region includes the write address hash, and based on the first determination: clearing the write history, storing the write address hash in the write history, and making a second determination that a wear level operation is due, and based on the second determination: performing the wear level operation.

Abstract: A generalized architecture for a highly available transaction processing system that combines commercially available components and software components specifically developed to implement the architecture into an integrated, highly available transaction processing system that minimizes planned and unplanned downtime, minimizes data loss in the event of failures, provides proactive monitoring of both hardware and software components of the highly available transaction processing system, provides automated recovery actions that involve fast failover, either locally to an Inactive Node, or remotely to a Standby Site, and provides an easy-to-use graphical-user-interface-based management interface that provides service-oriented views of the state of the system, with context-directed commands and meta-commands to guide managers in execution of their tasks.

Abstract: A method and apparatus performs high bandwidth low latency programmed I/O (PIO) write operations by passing tokens. A computer system in accordance with the present invention includes a plurality of CPUs, with each CPU coupled to a CPU agent. Each CPU agents is coupled to an interconnection fabric, which in turn is coupled to an I/O agent and memory. The computer system may also have multiple I/O agents. Each I/O agent is coupled to an I/O card, and the computer system may have multiple I/O cards. The CPU agents and the I/O agents have token slots, and tokens circulate between the token slots. When a CPU seeks to write to an I/O card, the CPU forwards a PIO write request to the CPU agent. If the CPU agent does not have the token, the CPU agent sends the write data along with a request for the token to the I/O agent. If the token is currently owned by the I/O agent, it is sent to the CPU agent.