Patents by Inventor Richard H. Womack
Richard H. Womack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8023308Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.Type: GrantFiled: September 14, 1990Date of Patent: September 20, 2011Assignee: National Semiconductor CorporationInventors: Joseph T. Evans, Jr., William D. Miller, Richard H. Womack
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Patent number: 8018754Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.Type: GrantFiled: September 14, 1990Date of Patent: September 13, 2011Assignee: National Semiconductor CorporationInventors: Joseph T. Evans, Jr., William D. Miller, Richard H. Womack
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Patent number: 7924599Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.Type: GrantFiled: November 29, 1989Date of Patent: April 12, 2011Assignee: Ramtron International CorporationInventors: Joseph T. Evans, Jr., William D. Miller, Richard H. Womack
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Patent number: 7672151Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.Type: GrantFiled: July 10, 1989Date of Patent: March 2, 2010Assignee: Ramtron International CorporationInventors: Joseph T. Evans, Jr., William D. Miller, Richard H. Womack
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Patent number: 6014053Abstract: An amplified MOS biasing apparatus and method for avoiding latch-up within an integrated circuit. An amplifier receives a plurality of voltages and multiplies the voltages by a gain so as to generate a plurality of amplified voltages. A comparator compares the plurality of voltages and generates signals indicating which is greatest and which is smallest. A switch connects the greatest of the voltages to N-wells in PMOS transistors and connects the smallest of the voltages to P-wells in NMOS transistors to discourage parasitic diodes, within the PMOS and NMOS transistors, from conducting excessive amounts of current.Type: GrantFiled: May 12, 1997Date of Patent: January 11, 2000Assignee: Philips Electronics North America CorporationInventor: Richard H. Womack
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Patent number: 5923212Abstract: A voltage divider is protected from current paths created by parasitic devices. The voltage divider includes a first string of diode-connected MOS transistors and a second string of diode-connected MOS transistors. A substrate bias terminal of each transistor in the first string is coupled to a substrate bias terminal of a corresponding transistor in the second string. The first string of transistors provides an output voltage which is protected from current paths created by parasitic devices.Type: GrantFiled: May 12, 1997Date of Patent: July 13, 1999Assignee: Philips Electronics North America CorporationInventor: Richard H. Womack
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Patent number: 5892255Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.Type: GrantFiled: October 12, 1997Date of Patent: April 6, 1999Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Richard H. Womack
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Patent number: 5679969Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.Type: GrantFiled: June 11, 1996Date of Patent: October 21, 1997Assignee: Radiant Technologies, Inc.Inventors: Joseph T. Evans, Jr., Richard H. Womack
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Patent number: 5541807Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.Type: GrantFiled: March 17, 1995Date of Patent: July 30, 1996Inventors: Joseph T. Evans, Jr., Richard H. Womack
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Patent number: 5434811Abstract: A non-volatile memory circuit comprises cross-coupled transistors which drive first and second nodes to differential voltage states. First and second ferroelectric capacitors are connected respectively between the first and second nodes and a common node. The ferroelectric capacitors are set to opposite polarization states as a function of the voltage states at the first and second differential nodes. When power is lost from the circuit, the last data state in the circuit is stored in the ferroelectric capacitors. When power is restored to the memory circuit, the ferroelectric capacitors unbalance the differential nodes to such an extent to cause the circuit to become reestablished to the last data state stored in the circuit. An input signal can be received at one of the nodes through an input transistor to set the state of the memory circuit and the state of the circuit can be read from one of the nodes through an output transistor. The input and output transistors can be the same device.Type: GrantFiled: May 24, 1989Date of Patent: July 18, 1995Assignee: National Semiconductor CorporationInventors: Joseph T. Evans, Jr., Richard H. Womack
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Patent number: 4800525Abstract: A scheme for addressing memory cells in random access memory arrays includes bit lines divided into a plurality of segments. Each pair of bit lines has a sense amp at each end coupled to both bit lines in the pair. Word lines address memory cells coupled to each bit line of the pair. When a pair of memory cells is accessed, the bit lines are electrically divided so that one memory cell is coupled to one sense amp through one bit line, and the other memory cell is coupled to the other sense amp through the other bit line. The memory cells can be coupled to the bit lines through segment lines, with each segment line connecting a subset of the memory cells to a bit line, in order to reduce capacitances presented to the sense amps. An alternating linear array of sense amps and bit line pairs can be used to increase overall density of the memory array by allowing sense amps to access more than one bit line pair. The bit lines are addressed so that each sense amp receives data from one one bit line pair at a time.Type: GrantFiled: August 6, 1987Date of Patent: January 24, 1989Assignee: Texas Instruments IncorporatedInventors: Ashwin H. Shah, Richard H. Womack, Chu-Ping Wang
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Patent number: 4750839Abstract: A semiconductor memory includes a memory array (10) that is operable to be addressed in either the page mode or the static column decode mode. A column address transparent latch (20) is provided which is controlled to either directly input a column address to a column decoder (26) or to latch the address in response to the generation of the column address strobe. A sequence detect circuit (30) detects the sequence to the row address strobe and the column address strobe to determine whether the page mode or the static column decode mode is generated. The sequence detect circuit (30) generates a Y-enable signal in a circuit (31) for control of the latch (20).Type: GrantFiled: August 7, 1985Date of Patent: June 14, 1988Assignee: Texas Instruments IncorporatedInventors: Chu-Ping Wang, Ashwin H. Shah, Richard H. Womack
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Patent number: 4713678Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.Type: GrantFiled: November 13, 1986Date of Patent: December 15, 1987Assignee: Texas Instruments IncorporatedInventors: Richard H. Womack, Sanjay K. Banerjee, Hisashi Shichijo, Satwinder Malhi
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Patent number: 4704705Abstract: A two transistor Dynamic Random Access Memory Cell and Array. Use of two pass transistors in series for the cell provides numerous additional capabilities for the DRAM array, and, in the preferred embodiment, provides bitline segment multiplexing, so that the sense amplifier pitch can be increased while the bitline capacitance as seen by the sense amplifier and by the memory cell is reduced. To accomplish this, the parasitic capacitance of the node between the two series pass transistors is kept to a minimum.Type: GrantFiled: July 19, 1985Date of Patent: November 3, 1987Assignee: Texas Instruments IncorporatedInventor: Richard H. Womack
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Patent number: 4581552Abstract: Power-up clear circuitry includes a latch which powers-up in a preferred state. Threshold detect circuitry changes the state of the latch when the supply voltage reaches its operating value, and then switches itself off. Transient protection circuitry ensures that the latch properly powers-up in the preferred state after a supply transient which drops below the threshold voltage of the circuit devices.Type: GrantFiled: February 17, 1984Date of Patent: April 8, 1986Assignee: Texas Instruments IncorporatedInventors: Richard H. Womack, Brock Barton, Robert Martin