Patents by Inventor Richard Hastie

Richard Hastie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11277455
    Abstract: A method including configuring a transmit process to store information including a queue of packets to be transmitted, the queue defining transmit process packets to be transmitted, each packet associated with a transmission time, and configuring a synchronization process to receive from the transmit process at least some of the information. The synchronization process performs one of: A) accessing a dummy send queue and a completion queue, and transmitting one or more of the transmit process packets in accordance with a completion queue entry in the completion queue, and B) sends a doorbell to transmission hardware at a time when at least one of the transmit process packets is to be transmitted, the synchronization process including a master queue configured to store transmission entries, each transmission entry including a transmit process indicator and an indication of transmit process packets to be transmitted. Related apparatus and methods are also described.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 15, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Alex Vainman, Natan Manevich, Nir Nitzani, Ilan Smith, Richard Hastie, Noam Bloch, Lior Narkis, Rafi Weiner
  • Patent number: 10516710
    Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: December 24, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan Levi, Idan Burstein, Shlomi Museri, Richard Hastie
  • Publication number: 20190379714
    Abstract: A method including configuring a transmit process to store information including a queue of packets to be transmitted, the queue defining transmit process packets to be transmitted, each packet associated with a transmission time, and configuring a synchronization process to receive from the transmit process at least some of the information. The synchronization process performs one of: A) accessing a dummy send queue and a completion queue, and transmitting one or more of the transmit process packets in accordance with a completion queue entry in the completion queue, and B) sends a doorbell to transmission hardware at a time when at least one of the transmit process packets is to be transmitted, the synchronization process including a master queue configured to store transmission entries, each transmission entry including a transmit process indicator and an indication of transmit process packets to be transmitted. Related apparatus and methods are also described.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 12, 2019
    Inventors: Dotan David Levi, Alex Vainman, Natan Manevich, Nir Nitzani, Ilan Smith, Richard Hastie, Noam Bloch, Lior Narkis, Rafi Weiner
  • Publication number: 20180234473
    Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.
    Type: Application
    Filed: March 30, 2017
    Publication date: August 16, 2018
    Inventors: Dotan Levi, Idan Burstein, Shlomi Museri, Richard Hastie