Abstract: A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

Abstract: Methods and apparatus are provided. In an example aspect, an amplifier protection circuit is provided. The amplifier protection circuit comprises an input for receiving a signal from a first amplifier, and an isolation circuit between the input and an output of the amplifier protection circuit. The isolation circuit is configured to sense a backward signal propagating from the output of the amplifier protection circuit towards the input to provide a sensed signal, and to provide at least one cancellation signal based on the sensed signal to at least partially cancel the backward signal.

Abstract: A feedforward amplifier comprises a power amplifier that generates an amplified signal, an error correcting circuitry that generates a first error signal and a second error signal based on an error in the amplified signal; and an output circuitry. The output circuitry comprises: a first quadrature coupler, an output of a first error amplifier is connected to the quadrature coupler and an input of the first error amplifier is configured to receive the first error signal, and an output of a second error amplifier is connected to the quadrature coupler and an input of the second error amplifier is configured to receive the second error signal. The output circuitry generates an error compensation signal in the first quadrature coupler from the output signals of the first and second error amplifiers.

Abstract: Methods and apparatus are provided. In an example aspect, a method of operating an amplifier circuit is provided. The amplifier circuit comprises a first amplifier configured to receive a first signal, a balanced amplifier comprising second and third amplifiers and configured to receive a second signal, and a first directional coupler. An output of the first amplifier is connected to a transmitted port of the first directional coupler, an output of the second amplifier is connected to an input port of the first directional coupler, an output of the third amplifier is connected to an isolated port of the first directional coupler, and a coupled port of the first directional coupler is connected to an output of the amplifier circuit.

Abstract: A power amplifier arrangement (100) for amplifying an input signal (Pin) to produce an output signal (Pout) is disclosed. The amplifier arrangement (100) comprise an input port (IN) for receiving the input signal; an output transmission line (110) having a first terminal (111) and a second terminal (112); an output port (OUT) coupled to the second terminal (112) of the output transmission line (110) for providing the output signal; and a plurality N of amplifying devices (121, 122, . . . 12N) distributed along the output transmission line (110). The power amplifier arrangement (100) is configured such that the plurality N of amplifying devices are active sequentially for amplifying the input signal with increasing amplitude of the input signal.

Abstract: Systems and methods for ultra-wideband Crest Factor Reduction (CFR) are provided. In some embodiments, a method performed by a wireless node for performing CFR includes performing a first CFR step on a plurality of input signals at a first sampling rate with joint peak detection and band-specific noise shaping; and performing a second CFR step on the resulting plurality of input signals at a second sampling rate with joint peak detection and joint noise shaping where the second sampling rate is higher than the first sampling rate. In this way, Peak-to-Average Power Ratio (PAPR) reduction may be increased while the computational complexity is reduced.

Abstract: Systems and methods for ultra-wideband Crest Factor Reduction (CFR) are provided. In some embodiments, a method performed by a wireless node for performing CFR includes performing a first CFR step on a plurality of input signals at a first sampling rate with joint peak detection and band-specific noise shaping; and performing a second CFR step on the resulting plurality of input signals at a second sampling rate with joint peak detection and joint noise shaping where the second sampling rate is higher than the first sampling rate. In this way, Peak-to-Average Power Ratio (PAPR) reduction may be increased while the computational complexity is reduced.

Abstract: An amplifier circuit for compensating an output signal provided at an output of the amplifier circuit comprises a cascade of sub-amplifiers. Each sub-amplifier of the cascade contributes to a respective part of the output signal. The cascade of sub-amplifiers comprises an end sub-amplifier and at least one preliminary sub-amplifier. At least one error correction block is coupled to apply feedforward error correction to an output of one of the at least one preliminary sub-amplifier.

Abstract: A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

Abstract: A power amplifier (100, 200, 500, 800, 1100) for amplifying an input signal into an output signal is disclosed. The power amplifier (100, 200, 500, 800, 1100) comprises an input port (110) for receiving the input signal and an output port (130) coupled to an output transmission line (140) for providing the output signal. The power amplifier (100, 200, 500, 800, 1100) further comprises multiple sets of sub-amplifiers (150, 160, 170, 180) distributed along the output transmission line, and inputs of the subamplifiers are coupled to the input port, outputs of the sub-amplifiers are coupled to the output transmission line. At least two different supply voltages are provided for the sub-amplifiers in the multiple sets of sub-amplifiers (150, 160, 170, 180).

Abstract: An amplifier circuit (200) for compensating an output signal provided at an output (212) of a circuit (210) is disclosed. The amplifier circuit (200) comprises an output transmission line (230) connected between the output (212) of the circuit (210) and an output port (240) and an amplifier (220). The amplifier (220) comprises multiple sub-amplifiers (221, 222, 223, 224), inputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled to an input transmission line (250) for receiving an error signal; and outputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled at respective places along the output transmission line (230) to inject a compensation signal to the output port (240). The error signal is derived from a reference input signal and the output signal of the circuit (210), and is amplified in the amplifier (220) into the compensation signal.

Abstract: An amplifier arrangement comprises N amplifier stages comprising a main amplifier stage and a plurality of peaking amplifier stages. A transmission line comprises a varying impedance for transforming a load impedance to a higher impedance at the main amplifier stage, wherein the plurality of peaking amplifiers are coupled at intermediate locations to the transmission line. The amplifier arrangement is configured such that at least two of the peaking amplifiers are collectively driven with time delayed versions of substantially the same signal. The amplifier arrangement may be configured to operate with N?2 or fewer transition points in a Doherty mode of operation. As such, the amplifier arrangement may comprise more amplifier stages than are necessarily required in a Doherty amplifier arrangement having the same number of transition points.

Abstract: An amplifier circuit for compensating an output signal provided at an output of the amplifier circuit comprises a cascade of sub-amplifiers. Each sub-amplifier of the cascade contributes to a respective part of the output signal. The cascade of sub-amplifiers comprises an end sub-amplifier and at least one preliminary sub-amplifier. At least one error correction block is coupled to apply feedforward error correction to an output of one of the at least one preliminary sub-amplifier.

Abstract: A composite power amplifier for amplification of an input signal into an output signal is disclosed. The composite power amplifier comprises an input port for receiving the input signal, and an output port for providing the output signal. Furthermore, the composite power amplifier comprises a first set of sub-amplifiers, comprising at least two sub-amplifiers, wherein the at least two sub-amplifiers are arranged along a taper of a first transmission line, wherein the first transmission line is connected to the first set of sub-amplifiers and the output port. Moreover, the composite power amplifier comprises a second set of sub-amplifiers, comprising at least two sub-amplifiers, wherein the at least two sub-amplifiers are arranged along a taper of a second transmission line, wherein the second transmission line is connected to the second set of sub-amplifiers and the output port.

Abstract: An amplifier arrangement comprises N amplifier stages (101 to 10N). The amplifier arrangement comprises a main cascade of quarter wavelength transmission lines coupled between an output of a main amplifier (102) of the N amplifier stages (101 to 10N) and an output node (15) of the amplifier arrangement, wherein the main cascade comprises N?1 quarter wavelength transmission lines (111 to 11N-1). An output of one peaking amplifier (10N) of the N amplifier stages is coupled to the output node (15), and remaining peaking amplifiers (101, 103 to 10N-1) of the N amplifier stages coupled to respective junctions (121 to 12N-2) in the main cascade of quarter wavelength transmission lines (111 to 11N-1).

Abstract: A driver circuit for a composite power amplifier configured to operate in at least one Chireix-mode a first and a second sub-amplifier for amplification of an input signal into an output signal is disclosed. An input network of the driver circuit comprises a means configured to provide a first signal which is linearly derivable from the input signal, and a second signal which is non-linearly derivable from the input signal. The input network combines the first signal, at zero degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a first feeding signal for the first sub-amplifier. Furthermore, the input network combines the first signal, at 180 degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a second feeding signal for the second sub-amplifier.

Abstract: A modular power amplifier system and an electronic device comprising the modular power amplifier system in which, the modular power amplifier system comprises a plurality of amplifier modules. The plurality of amplifier modules are arranged into a number of sections comprising a first section which comprises a first amplifier module configured to receive the input signal within a first amplitude range and provide an output signal having a first output power; a second section which comprises a second amplifier module configured to receive the input signal within a second amplitude range and provide an output signal having a second output power; and an i-th section which comprises multiple amplifier modules, each being configured to receive the input signal within a certain amplitude range and provide an output signal having a certain output power. The output signals of the amplifier modules are combined to provide output signals with scalable output power.

Abstract: A power amplifier (100, 200, 500, 800, 1100) for amplifying an input signal into an output signal is disclosed. The power amplifier (100, 200, 500, 800, 1100) comprises an input port (110) for receiving the input signal and an output port (130) coupled to an output transmission line (140) for providing the output signal. The power amplifier (100, 200, 500, 800, 1100) further comprises multiple sets of sub-amplifiers (150, 160, 170, 180) distributed along the output transmission line, and inputs of the subamplifiers are coupled to the input port, outputs of the sub-amplifiers are coupled to the output transmission line. At least two different supply voltages are provided for the sub-amplifiers in the multiple sets of sub-amplifiers (150, 160, 170, 180).

Abstract: An amplifier circuit (200) for compensating an output signal provided at an output (212) of a circuit (210) is disclosed. The amplifier circuit (200) comprises an output transmission line (230) connected between the output (212) of the circuit (210) and an output port (240) and an amplifier (220). The amplifier (220) comprises multiple sub-amplifiers (221, 222, 223, 224), inputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled to an input transmission line (250) for receiving an error signal; and outputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled at respective places along the output transmission line (230) to inject a compensation signal to the output port (240). The error signal is derived from a reference input signal and the output signal of the circuit (210), and is amplified in the amplifier (220) into the compensation signal.

Abstract: An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.