Abstract: A 3D body scanner for generating 3D body models includes a depth sensor for acquiring depth data of a field of view and a control unit that controls the 3D body scanner and processes the depth data. The control unit can extract body characteristics of a person from the acquired depth data and can compare the extracted body characteristics of the person with body characteristics of already registered users and activate the processing and recording of the depth data from the depth sensor when the comparison determines that the person is a registered user.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Abstract: A method and apparatus for testing complex processor-based computer modules and their associated computer systems by allowing the normal initialization path between a memory component storing code utilized during initialization and the processor to be interrupted and test code from an external test system to be substituted for initialization code. Following initialization, a two-way communication link between the processor and the test system is created to allow interactive testing and status reporting. The testing method and apparatus maximizes the likelihood of precisely identifying defects on the module under test.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.