Abstract: An electrolytic plating composition for superfilling submicron features in a semiconductor integrated circuit device and a method of using the same. The composition comprises (a) a source of copper ions to electrolytically deposit copper onto the substrate and into the electrical interconnect features, and (b) a suppressor comprising at least three amine sites, said polyether comprising a block copolymer substituent comprising propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units, wherein the number average molecular weight of the suppressor compound is between about 1,000 and about 20,000.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor; and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor; and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor, and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: An electrolytic plating composition for superfilling submicron features in a semiconductor integrated circuit device and a method of using the same. The composition comprises (a) a source of copper ions to electrolytically deposit copper onto the substrate and into the electrical interconnect features, and (b) a suppressor comprising at least three amine sites, said polyether comprising a block copolymer substituent comprising propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units, wherein the number average molecular weight of the suppressor compound is between about 1,000 and about 20,000.

Abstract: An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor, and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a a quaternized pyridinium salt compound for leveling.

Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a quaternized pyridinium salt compound for leveling.

Abstract: In electrolytic copper plating, an aqueous composition comprising a source of copper ions and at least one alkylene or polyalkylene glycol monoether which is soluble in the aqueous phase and has molecular weight not greater than about 500 for improving the efficacy of other additives such as, for example, levelers and suppressors; and a related plating method.

Abstract: A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate having submicron-sized features, and a concentrate for forming a corresponding electroplating bath. A substrate is immersed into an electroplating bath formed from the concentrate including ionic copper and an effective amount of a defect reducing agent, and electroplating the copper deposit from the bath onto the substrate to fill the submicron-sized reliefs. The occurrence of protrusion defects from superfilling, surface roughness, and voiding due to uneven growth are reduced, and macro-scale planarity across the wafer is improved.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device involving and electrolytic solution containing a source of Cu ions and a quaternized pyridinium salt compound for leveling.

Abstract: A method and composition for electroplating Cu onto a substrate in the manufacture of a microelectronic device. The plating composition comprises an electrolytic solution containing a source of Cu ions and a substituted pyridyl polymer compound for leveling.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate. The method comprises immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1; and supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.

Abstract: An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.