Patents by Inventor Richard I. Baum

Richard I. Baum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8321637
    Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection, of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Thomas J. Heller, Jr.
  • Patent number: 7484043
    Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Heller, Jr., Richard I. Baum, Michael Ignatowski, James W. Rymarczyk
  • Publication number: 20080288727
    Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection, of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard I. Baum, Thomas J. Heller, JR.
  • Publication number: 20080147988
    Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.
    Type: Application
    Filed: February 26, 2008
    Publication date: June 19, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Heller, Richard I. Baum, Michael Ignatowski, James W. Rymarczyk
  • Publication number: 20040268044
    Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.
    Type: Application
    Filed: June 25, 2003
    Publication date: December 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: Thomas J. Heller, Richard I. Baum, Michael Ignatowski, James W. Rymarczyk
  • Patent number: 5619713
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: April 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5590362
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: December 31, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5548769
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: August 20, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5537604
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized. functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5537603
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5537622
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5530883
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: June 25, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5423013
    Abstract: Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: June 6, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Brent A. Carlson, Moon J. Kim, Michael G. Mall, Casper A. Scalzi, Bhaskar Sinha
  • Patent number: 5381537
    Abstract: A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results.
    Type: Grant
    Filed: December 6, 1991
    Date of Patent: January 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Kenneth E. Plambeck, Casper A. Scalzi, Richard J. Schmalz, Bhaskar Sinha
  • Patent number: 5220669
    Abstract: A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: June 15, 1993
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Terry L. Borden, Carol E. Clark, Alan G. Ganek, James Lum, Michael G. Mall, Casper A. Scalzi, Richard J. Schmalz
  • Patent number: 5210870
    Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
    Type: Grant
    Filed: March 27, 1990
    Date of Patent: May 11, 1993
    Assignee: International Business Machines
    Inventors: Richard I. Baum, Glen A. Brent, Donald H. Gibson, David B. Lindquist
  • Patent number: 5166674
    Abstract: A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which includes a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the swithc reverses the source and destination field and returns the packet to the sender with an error flag.
    Type: Grant
    Filed: June 21, 1991
    Date of Patent: November 24, 1992
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Charles H. Brotman, James W. Rymarczyk
  • Patent number: 5161156
    Abstract: A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch reverses the source and destination field and returns the packet to the sender with an error flag.
    Type: Grant
    Filed: February 2, 1990
    Date of Patent: November 3, 1992
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Charles H. Brotman, James W. Rymarczyk
  • Patent number: 5023773
    Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.
    Type: Grant
    Filed: February 10, 1988
    Date of Patent: June 11, 1991
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Terry L. Borden, Justin R. Butwell, Carl E. Clark, Alan G. Ganek, James Lum, Michael G. Mall, David R. Page, Kenneth E. Plambeck, Casper A. Scalzi, Richard J. Schmalz
  • Patent number: 4979098
    Abstract: A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE.
    Type: Grant
    Filed: June 8, 1990
    Date of Patent: December 18, 1990
    Assignee: International Business Machines Corporation
    Inventors: Richard I. Baum, Terry L. Borden, Justin R. Butwell, Carl E. Clark, Alan G. Ganek, James Lum, Michael G. Mall, Kenneth E. Plambeck, Casper A. Scalzi, Richard J. Schmalz, Ronald M. Smith, Julian Thomas