Patents by Inventor Richard I. Mellitz
Richard I. Mellitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210289617Abstract: Methods and apparatus to facilitate routing of high-speed data channels are described herein. Under one aspect, a high-speed data channel is routed between an integrated circuit (IC) and a high-speed data connector mounted to a multilayer printed circuit board as part of a circuit assembly. The circuit assembly includes a signal pathway providing a high-speed data channel from the integrated circuit to the high-speed data connector, wherein a portion of the signal pathway includes an axial cable, such as a twin axial cable. The high-speed data channel may comprise a multi-lane data channel and may be bi-directional.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Richard I. MELLITZ, Brandon GORE, Beom-Taek LEE
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Publication number: 20190200450Abstract: Methods and apparatus for utilizing flexible (flex) circuit technology and/or axial cable to facilitate routing of high-speed data channels are described herein. Under one aspect, a high-speed data channel if routed between an integrated circuit (IC) and a high-speed data connector mounted to a multilayer printed circuit board as part of a circuit assembly. The circuit assembly includes a signal pathway providing a high-speed data channel from the integrated circuit to the high-speed data connector, wherein a portion of the signal pathway includes a flex circuit or axial cable.Type: ApplicationFiled: September 19, 2017Publication date: June 27, 2019Applicant: Intel CorporationInventors: Richard I. MELLITZ, Brandon GORE, Beom-Taek LEE
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Patent number: 10164912Abstract: Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.Type: GrantFiled: July 25, 2016Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Adee O. Ran, David L. Chalupsky, Kevan A. Lillie, Richard I. Mellitz, Kent C. Lusted
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Publication number: 20180026917Abstract: Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.Type: ApplicationFiled: July 25, 2016Publication date: January 25, 2018Inventors: Adee O. Ran, David L. Chalupsky, Kevan A. Lillie, Richard I. Mellitz, Kent C. Lusted
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Patent number: 9846189Abstract: Examples are disclosed for characterizing a transmission line. Sets of scatter parameters (s-parameters) associated with measured or modeled insertion loss (IL) or return loss (RL) values over a range of frequencies may be acquired for a transmission line. One or more parameter values for use in IL or RL fit functions may be adjusted to reach a threshold for a coefficient of determination (R2) value of a curve generated using the IL or RL fit functions to approximate the set of s-parameters over the range of frequencies. The IL or RL fit functions may then be used to generate other sets of s-parameters associated with IL or RL values for a recreated model of the transmission line. The other sets of s-parameters may be scaled to characterize transmission lines of various lengths. Other examples are described and claimed.Type: GrantFiled: January 22, 2014Date of Patent: December 19, 2017Assignee: INTEL CORPORATIONInventor: Richard I. Mellitz
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Publication number: 20160099795Abstract: Technologies for capabilities exchange include a network port logic having a communication link coupled to a remote link partner. The port logic transmits local host loss information to the link partner and receives remote host loss information from the link partner. The port logic may communicate the host loss information via an autonegotiation base page, an autonegotiation next page, or a PMD control frame. The port logic determines total channel loss based on the local host loss, the remote host loss, and cable loss. The port logic may bring the communication link up without forward error correction (FEC) if the total channel loss is less than a FEC limit, may bring the link up with FEC if the total loss is less than a specification limit, or may not bring the link up if the total channel loss is above the specification limit. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2014Publication date: April 7, 2016Inventors: Kent C. Lusted, Adee O. Ran, Richard I. Mellitz
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Publication number: 20150204927Abstract: Examples are disclosed for characterizing a transmission line. Sets of scatter parameters (s-parameters) associated with measured or modeled insertion loss (IL) or return loss (RL) values over a range of frequencies may be acquired for a transmission line. One or more parameter values for use in IL or RL fit functions may be adjusted to reach a threshold for a coefficient of determination (R2) value of a curve generated using the IL or RL fit functions to approximate the set of s-parameters over the range of frequencies. The IL or RL fit functions may then be used to generate other sets of s-parameters associated with IL or RL values for a recreated model of the transmission line. The other sets of s-parameters may be scaled to characterize transmission lines of various lengths. Other examples are described and claimed.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Inventor: RICHARD I. MELLITZ
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Patent number: 8370704Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.Type: GrantFiled: March 9, 2009Date of Patent: February 5, 2013Assignee: Intel CorporationInventors: Ilango S. Ganga, Richard I. Mellitz
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Publication number: 20100229067Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.Type: ApplicationFiled: March 9, 2009Publication date: September 9, 2010Inventors: Ilango S. Ganga, Richard I. Mellitz
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Patent number: 7076401Abstract: A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.Type: GrantFiled: April 30, 2002Date of Patent: July 11, 2006Assignee: Intel CorporationInventor: Richard I. Mellitz
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Publication number: 20030204793Abstract: A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.Type: ApplicationFiled: April 30, 2002Publication date: October 30, 2003Inventor: Richard I. Mellitz
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Patent number: 6624690Abstract: An apparatus includes a circuit and a signal source to supply a trigger signal to the circuit. The signal source is adapted to supply the trigger signal such that a reflection of the trigger signal delays the time at which the circuit is triggered.Type: GrantFiled: November 24, 1999Date of Patent: September 23, 2003Assignee: Intel CorporationInventor: Richard I. Mellitz
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Patent number: 6421391Abstract: A transmission line for a clock input for a digital device. In the prior art, a clock signal was fed to a digital device on a transmission line. It was found that, when the clock frequency was doubled, the clock pulses received by the device became unacceptable. The invention lengthened the transmission line, rather than shortening it, and thereby removed the unacceptable features of the clock pulses.Type: GrantFiled: September 22, 1997Date of Patent: July 16, 2002Assignee: NCR CorporationInventor: Richard I. Mellitz
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Publication number: 20020033719Abstract: An apparatus includes a circuit and a signal source to supply a trigger signal to the circuit. The signal source is adapted to supply the trigger signal such that a reflection of the trigger signal delays the time at which the circuit is triggered.Type: ApplicationFiled: November 24, 1999Publication date: March 21, 2002Inventor: RICHARD I. MELLITZ
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Patent number: 6078965Abstract: A branched transmission line, used for delivering control signals to integrated memory circuits. Memory circuits require control signals, which are delivered on control lines. If multiple memory circuits are involved, multiple control lines are used. If the multiple control lines branch from a common branch point on a supply line, undesirable reflections can occur. The invention reduces the reflections, by distributing the branching, as by starting with three initial branches, each of which branches into three other branches, in order to feed nine memory circuits.Type: GrantFiled: December 8, 1997Date of Patent: June 20, 2000Assignee: Intel CorporationInventors: Richard I. Mellitz, Roy M. Stevens
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Patent number: 5990721Abstract: A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.Type: GrantFiled: August 18, 1997Date of Patent: November 23, 1999Assignee: NCR CorporationInventor: Richard I. Mellitz
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Patent number: 5825630Abstract: A computer baseboard providing localized support for high pin count, high density components. The baseboard includes a first circuit board capable of supporting low pin count electrical components. The first circuit board has a surface onto which the low pin count electrical components are mounted, and an area to which a second, smaller, circuit board is connected in a parallel arrangement with the first circuit board. The second circuit board has a first surface onto which high pin count electrical components are mounted, and a second surface physically and electrically connected to the area on said first substrate. The first and second circuit boards together provide support for electrical components having higher pin counts and densities than the first circuit board can support individually, such as high performance microprocessors and chipsets.Type: GrantFiled: November 7, 1996Date of Patent: October 20, 1998Assignee: NCR CorporationInventors: Billy K. Taylor, Richard I. Mellitz
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Patent number: 5596283Abstract: Electrical test method and apparatus for performing the method. The method operates to determine an electrical characteristic of a node (2) disposed upon a surface of a substrate (3), such as a printed wiring board (PWB). The method includes a first step of providing relative motion between a probe (1) and the surface of the PWB. A second step measures the electrical characteristic during a time that there is relative motion between the probe and the surface of the PWB. In one embodiment of the invention the step of measuring measures capacitance while in another embodiment of the invention the step of measuring measures charge capacity. The step of providing relative motion, in one embodiment of the invention, includes the steps of maintaining the PWB stationary while linearly translating the probe over the surface. In another embodiment of the invention the step of providing relative motion includes the steps of maintaining the probe stationary while moving the PWB.Type: GrantFiled: December 19, 1995Date of Patent: January 21, 1997Assignee: Digital Equipment CorporationInventors: Richard I. Mellitz, Michael V. Dowd
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Patent number: 5498965Abstract: Method for determining the characteristic impedance of a transmission line on a printed wiring board using time domain reflectometry. The method involves selecting a driving point in time, selecting an undisturbed interval, measuring voltage at predetermined time intervals across the undisturbed interval, determining from the measured voltages a curve representative of such voltages, and determining the voltage on the representative curve at the driving point. The characteristic impedance of the transmission line under test, denoted by Z.sub.0, is obtained by using the "driving point" of the transmission line as the reference plane for the impedance measurements.Type: GrantFiled: December 15, 1993Date of Patent: March 12, 1996Assignee: Digital Equipment CorporationInventor: Richard I. Mellitz
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Patent number: 5256975Abstract: A hand-held test probe is employed which uses a capacitance measuring circuit to measure capacitance as the probe is scanned along a pattern of conductors (pads or pins) at a steady rate. The capacitance measurement is stored in a memory during the scan, then maximums are detected in the stored data, corresponding to the conductor pattern. If a particular conductor has a short or a break in continuity, its capacitance will be more or less than it should be. The detected maximums are compared with recorded values for a known-good printed wiring board for this scan pattern. If the comparison shows a difference greater than a selected threshold, an error is indicated for this pin location. The known-good is scanned in a "learn" mode, in which the capacitance values are stored for each scan, identified by scan number.Type: GrantFiled: June 1, 1992Date of Patent: October 26, 1993Assignee: Digital Equipment CorporationInventors: Richard I. Mellitz, Ellsworth W. Stearns