Patents by Inventor Richard Illman

Richard Illman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060252405
    Abstract: A method and apparatus for filtering interference signals to and from a broadband over power line system. The apparatus includes fixed notch filters and adaptive notch filters that filter interference signals that are generated and received by the system. The fixed filters are used for known interference signals, and the adaptive notch filters are used to filter unknown interference signals that are detected over time. The notch filters are configured at both a bridge and client of the system that send and receive broadband signals.
    Type: Application
    Filed: May 8, 2006
    Publication date: November 9, 2006
    Inventors: John Matz, Richard Illman
  • Patent number: 6845479
    Abstract: A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FN and then forming a vector set TN?1 and then simulating the vector set TN?1 against the fault list FN. Any vector from the set TN?1 which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set TF.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: January 18, 2005
    Assignee: Tality UK Limited
    Inventor: Richard Illman
  • Publication number: 20020133776
    Abstract: A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FN and then forming a vector set TN−1 and then simulating the vector set TN−1 against the fault list FN. Any vector from the set TN−1 which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set Tt.
    Type: Application
    Filed: March 14, 2001
    Publication date: September 19, 2002
    Inventor: Richard Illman