Patents by Inventor Richard J. Bono

Richard J. Bono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711424
    Abstract: A low thermal stress package for large area semiconductor dies. The package may include a substrate and at least one pedestal extending from the substrate, wherein the pedestal may have a mounting surface that is smaller than a mounting surface of a semiconductor die that is mounted to the pedestal. The bonded area between the die and the pedestal is therefore reduced relative to conventional semiconductor package substrates, as is the amount of thermal stress sustained by the die during thermal cycling.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 18, 2017
    Assignee: Littelfuse, Inc.
    Inventors: Richard J. Bono, Neil Solano
  • Publication number: 20160141275
    Abstract: An electronic power module is disclosed. The module includes a baseplate and a plurality of internally isolated discrete electronic devices mounted to the baseplate such that their electrical leads are oriented away from the baseplate. Electrical leads may be coupled to a printed circuit board (PCB). Other features disclosed include a thermal interface material and an application-specific heat sink. The assembly may be overmolded via injection molding or potted using an encapsulant. Example electronic devices include thyristors, diodes, and transistors.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 19, 2016
    Applicant: LITTELFUSE, INC.
    Inventors: Richard J. Bono, Koichiro Yoshimoto
  • Publication number: 20140077378
    Abstract: A low thermal stress package for large area semiconductor dies. The package may include a substrate and at least one pedestal extending from the substrate, wherein the pedestal may have a mounting surface that is smaller than a mounting surface of a semiconductor die that is mounted to the pedestal. The bonded area between the die and the pedestal is therefore reduced relative to conventional semiconductor package substrates, as is the amount of thermal stress sustained by the die during thermal cycling.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 20, 2014
    Applicant: LITTELFUSE, INC.
    Inventors: Richard J. Bono, Neil Solano