Abstract: In an example, the present invention provides a method of forming a semiconductor device on a gallium and nitrogen containing material. The method includes providing a substrate member comprising a surface region, the substrate member comprising a gallium and nitrogen bearing material. The method includes causing an implanted species to electrically activate the implant profile while removing one or more crystalline damage from the epitaxial material to change the amorphous state to a single crystalline state, and thereby creating a substantially electrically activated crystalline material.

Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: Light Emitting Diodes (LEDs) made with GaN and related materials are used to realize high efficiency devices which emit visible radiation. These GaN-based LEDs consists of a multi-layer structure which include p-type electron confinement layers, and p-type current spreading and ohmic contacts layers located above the active region. The alignment of the etched features which penetrate near or through the active region and the ohmic contact is critical and is currently a technological challenge in the fabrication process. Any errors in this alignment and successive layers will short across the active layers of the device and result in reduced yield of functional devices. The invention described herein provides a method and apparatus to realize the successful alignment and streamlined fabrication of high-density LED array devices. The result is a higher pixel density GaN-based LED device with higher current handling capability resulting in a brighter device of the same area.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p? type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: Light Emitting Diodes (LEDs) made with GaN and related materials are used to realize high efficiency devices which emit visible radiation. These GaN-based LEDs consists of a multi-layer structure which include p-type electron confinement layers, and p-type current spreading and ohmic contacts layers located above the active region. The alignment of the etched features which penetrate near or through the active region and the ohmic contact is critical and is currently a technological challenge in the fabrication process. Any errors in this alignment and successive layers will short across the active layers of the device and result in reduced yield of functional devices. The invention described herein provides a method and apparatus to realize the successful alignment and streamlined fabrication of high-density LED array devices. The result is a higher pixel density GaN-based LED device with higher current handling capability resulting in a brighter device of the same area.

Abstract: Light Emitting Diodes (LEDs) made with GaN and related materials are used to realize high efficiency devices which emit visible radiation. These GaN-based LEDs consists of a multi-layer structure which include p-type electron confinement layers, and p-type current spreading and ohmic contacts layers located above the active region. The alignment of the etched features which penetrate near or through the active region and the ohmic contact is critical and is currently a technological challenge in the fabrication process. Any errors in this alignment and successive layers will short across the active layers of the device and result in reduced yield of functional devices. The invention described herein provides a method and apparatus to realize the successful alignment and streamlined fabrication of high-density LED array devices. The result is a higher pixel density GaN-based LED device with higher current handling capability resulting in a brighter device of the same area.

Abstract: A low-fitting hairline cap is disclosed. The cap includes an indentation on each side that extends upward relative to the body. The indentations enable a wearer of the cap to seat the cap in a lower position on the head without being obstructed by the upper ears.

Abstract: Disclosed is a multi-tool assembly system and associated methods for threading small spheres or other objects with through-holes onto small diameter wire or fiber, trimming excess wire, and securing them in position with adhesive. The tools can precisely manipulate objects having diameters of less than 25 microns in a reliable, repeatable manner and may operate semi-autonomously, fully autonomously, or in a manual mode.

Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material.

Abstract: A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas.

Abstract: A vertical field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.