Patents by Inventor Richard J. Eickemeyer
Richard J. Eickemeyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886883Abstract: A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.Type: GrantFiled: August 26, 2021Date of Patent: January 30, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Brian D. Barrick, Richard J. Eickemeyer, John B Griswell, Jr., Balaram Sinharoy, Brian W. Thompto, Ophir Erez
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Patent number: 11868773Abstract: A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.Type: GrantFiled: January 6, 2022Date of Patent: January 9, 2024Assignee: International Business Machines CorporationInventors: Steven J. Battle, Brian D. Barrick, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy, Brian W. Thompto, Tu-An T. Nguyen
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Patent number: 11847458Abstract: Methods and systems for determining a priority of a threads is described. A processor can execute branch instructions of the thread. The processor can predict branch instruction outcomes of the branch instructions of the thread. The processor can increment a misprediction count of the thread in response to an actual execution of a branch instruction of the thread being different from a corresponding branch instruction prediction outcome of the thread. The processor can determine the priority of the thread based on the misprediction count of the thread.Type: GrantFiled: July 2, 2021Date of Patent: December 19, 2023Assignee: International Business Machines CorporationInventors: Richard J. Eickemeyer, Ehsan Fatehi, John B. Griswell, Jr., Naga P. Gorti
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Patent number: 11709676Abstract: Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.Type: GrantFiled: August 19, 2021Date of Patent: July 25, 2023Assignee: International Business Machines CorporationInventors: Steven J. Battle, Brian D. Barrick, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy, Brian W. Thompto, Tu-An T. Nguyen
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Publication number: 20230214218Abstract: A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.Type: ApplicationFiled: January 6, 2022Publication date: July 6, 2023Inventors: Steven J. Battle, Brian D. Barrick, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, JR., Balaram Sinharoy, Brian W. Thompto, Tu-An T. Nguyen
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Patent number: 11663013Abstract: A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.Type: GrantFiled: August 24, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, Jr., Balaram Sinharoy, Brian W. Thompto, Ophir Erez
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Publication number: 20230060910Abstract: A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.Type: ApplicationFiled: August 24, 2021Publication date: March 2, 2023Inventors: Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, JR., Balaram Sinharoy, Brian W. Thompto, Ophir Erez
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Publication number: 20230063079Abstract: A computer processor includes an instruction pipeline configured to dispatch a plurality of branch-to-count (BCNT) instructions and an instruction fetch unit (IFU). The IFU is configured to execute an instruction loop for fetching a targeted number of BCNT instructions from the instruction pipeline and to monitor a loop counter that counts a number of fetched BCNT instructions that are actually fetched from the instruction pipeline in response to executing the instruction loop. The IFU resolves a final BCNT instruction included in the instruction loop in response to the number of fetched BCNT instructions reaching a target loop count value.Type: ApplicationFiled: August 24, 2021Publication date: March 2, 2023Inventors: Mehul Patel, Nicholas R. Orzol, Dung Q. Nguyen, Balaram Sinharoy, Richard J. Eickemeyer, John B. Griswell, Jr., Brian W. Thompto
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Publication number: 20230068640Abstract: A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Nicholas R. Orzol, Mehul Patel, Dung Q. Nguyen, Brian D. Barrick, Richard J. Eickemeyer, John B. Griswell, JR., Balaram Sinharoy, Brian W. Thompto, Ophir Erez
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Publication number: 20230053981Abstract: Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Inventors: Steven J. Battle, Brian D. Barrick, Dung Q. Nguyen, Richard J. Eickemeyer, John B. Griswell, JR., Balaram Sinharoy, Brian W. Thompto, Tu-An T. Nguyen
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Publication number: 20230004394Abstract: Methods and systems for determining a priority of a threads is described. A processor can execute branch instructions of the thread. The processor can predict branch instruction outcomes of the branch instructions of the thread. The processor can increment a misprediction count of the thread in response to an actual execution of a branch instruction of the thread being different from a corresponding branch instruction prediction outcome of the thread. The processor can determine the priority of the thread based on the misprediction count of the thread.Type: ApplicationFiled: July 2, 2021Publication date: January 5, 2023Inventors: Richard J. Eickemeyer, Ehsan Fatehi, John B. Griswell, JR., Naga P. Gorti
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Patent number: 11520591Abstract: Processing data in an information handling system is disclosed that includes: in response to an event that triggers a flushing operation, calculate a finish ratio, wherein the finish ratio is a number of finished operations to a number of at least one of the group consisting of in-flight instructions, instructions pending in a processor pipeline, instructions issued to an issue queue, and instructions being processed in a processor execution unit; compare the calculated finish ratio to a threshold; and if the finish ratio is greater than the threshold, then do not perform the flushing operation. Also disclosed is moving the flush point.Type: GrantFiled: March 27, 2020Date of Patent: December 6, 2022Assignee: International Business Machines CorporationInventors: Ehsan Fatehi, Richard J. Eickemeyer, John B. Griswell, Jr.
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Publication number: 20210303311Abstract: Processing data in an information handling system is disclosed that includes: in response to an event that triggers a flushing operation, calculate a finish ratio, wherein the finish ratio is a number of finished operations to a number of at least one of the group consisting of in-flight instructions, instructions pending in a processor pipeline, instructions issued to an issue queue, and instructions being processed in a processor execution unit; compare the calculated finish ratio to a threshold; and if the finish ratio is greater than the threshold, then do not perform the flushing operation. Also disclosed is moving the flush point.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Ehsan Fatehi, Richard J. Eickemeyer, John B. Griswell, JR.
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Patent number: 10942743Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: GrantFiled: April 28, 2020Date of Patent: March 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Patent number: 10915446Abstract: Techniques are disclosed for identifying data streams in a processor that are likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level and a memory resource utilization threshold.Type: GrantFiled: November 23, 2015Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Richard J. Eickemeyer, John B. Griswell, Jr., Mohit S. Karve
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Patent number: 10795683Abstract: Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting a more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache.Type: GrantFiled: June 11, 2014Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan, Mauricio J. Serrano
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Publication number: 20200257535Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Patent number: 10725783Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: GrantFiled: November 2, 2018Date of Patent: July 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Patent number: 10664279Abstract: Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.Type: GrantFiled: January 4, 2019Date of Patent: May 26, 2020Assignee: International Business Machines CorporationInventors: Richard J. Eickemeyer, Sheldon Levenstein, David S. Levitan, Mauricio J. Serrano
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Publication number: 20200142702Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske