Patents by Inventor Richard J. Evans
Richard J. Evans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240382192Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a repair site. In one embodiment, a repair device is delivered with a delivery device system configured to move a cartridge with the repair device disposed therein toward an anvil with soft tissue positioned thereon. The delivery device linearly moves the cartridge toward the anvil with a worm drive positioned within a housing by rotating a thumb wheel disposed around the worm drive. Such linear movement is provided with a finger element extending from the worm drive that is configured to cooperate with an internal surface of the thumb wheel. With this arrangement, upon rotating the thumb wheel, the worm drive rotates with the finger element engaged with the internal surface of the thumb wheel to linearly move the cartridge toward the anvil.Type: ApplicationFiled: May 14, 2024Publication date: November 21, 2024Inventors: Erik N. Kubiak, Roy M. Taylor, Zackery K. Evans, Richard J. Linder, Scott D. Miles, Tyler J. Cole, Kent F. Beck
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Publication number: 20240369847Abstract: A component for a wearable electronic device can include a housing defining an internal volume, a first connector that is removably attachable to a head-mounted display. the first connector configured to electrically connect to the head-mounted display. and a second connector that is removably attachable to a supplemental unit. the second connector configured to electrically connect to the supplemental unit. The component can include a stiffener disposed in the internal volume, and the stiffener can be flexible along a first axis and rigid along two axes that are perpendicular to the first axis and to each other. An operational component can be disposed in the internal volume, and the operational component can be electrically connected to at least one of the first connector or the second connector.Type: ApplicationFiled: July 27, 2022Publication date: November 7, 2024Inventors: Kendall L. Helbert, Heidi Williamson, James W. Vandyke, Neal D. Evans, Nikolas T. Vitt, Samuel G. Smith, Nicolas Lylyk, Richard P. Howarth, Trevor J. Ness, Darshan R. Kasar, Muhammad F. Hossain, Christopher S. Graham, Daniel C. Wagman
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Publication number: 20240341756Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a repair site. In one embodiment, a repair device includes a plate member and an anchor. The plate member having a periphery, the plate member configured to be positioned along an outer surface of the soft tissue. The anchor includes a base and six legs extending from the base, the six legs extending from the base being moveable to a curled configuration such that the six legs wrap around separate portions of the periphery of the plate member with the soft tissue therebetween. In this manner, the repair device may be anchored to the soft tissue.Type: ApplicationFiled: April 16, 2024Publication date: October 17, 2024Inventors: Richard J. Linder, Erik N. Kubiak, Roy M. Taylor, Zackery K. Evans, Tyler J. Cole, Scott D. Miles, Kent F. Beck
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Publication number: 20240325138Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a soft tissue repair site. In one embodiment, a repair device configured to couple to soft tissue is provided. The repair device includes a capture portion and an anchor portion. The capture portion configured to extend with radial portions. The anchor portion includes a base with multiple legs extending therefrom. The multiple legs are configured to move from a linear position to a formed position such that, in the formed position, the multiple legs couple to structure of the capture portion.Type: ApplicationFiled: March 28, 2024Publication date: October 3, 2024Inventors: Erik N. Kubiak, Roy M. Taylor, Zackery K. Evans, Cody L. Gehrke, Daniel K. Smith, Richard J. Linder, Scott D. Miles, Tyler J. Cole
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Patent number: 12051107Abstract: A method for presenting pre-approved and pre-underwritten offers to a customer may include: receiving targeting criteria based on at least one of current accounts with the financial institution, assets, creditworthiness, and credit risk for an offer for a financial product; identifying a target population of customers for the offer by applying the targeting criteria to a population of customers; reviewing each customer in the target population for underwriting for the financial product based on inferred income for each customer and accounts that each customer has with the financial institution, wherein the underwriting is performed before the financial product is offered; determining a channel to present the offer to one of the customers that passed underwriting; communicating the offer to the customer over the selected channel; and providing an accepted offer to a fulfilment engine, wherein the fulfilment engine initiates an account opening for the financial product.Type: GrantFiled: March 17, 2023Date of Patent: July 30, 2024Assignee: JPMORGAN CHASE BANK , N.A.Inventors: W. David Thomas, Claimonte Nelson, Dennis Bowers, Michael S. Hartman, Steven Noel Roth, Jagan Devisetty, Nagesh Chalasani, Jason J. Kim, Marianna Dulkina, Suzanne Dimant, Vakul Garg, Ajit Nalla, Daniel A. Haas, James Hennessey, Keith Reichenbach, Richard S. Bunke, Seth Goldkrantz, Stephani L. Breault, Steven Aller, Vidyasankar Narayanan, Wade A. Stratton, Margaret F. Evans, Kapil Bansal
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Patent number: 11656108Abstract: An example sensor includes a PCB mounted in an internal chamber of housing, wherein the PCB comprises calibration electrical contact points; a sealing grommet mounted in the internal chamber, wherein the sealing grommet comprises an axial hole aligned with the calibration electrical contact points, thereby providing access to the calibration electrical contact points of the PCB; a grommet plug disposed in the axial hole of the sealing grommet; a sensing element disposed in the housing and electrically-coupled to the PCB via an electrical connection; an encapsulant sealing material deposited on the sealing grommet and the grommet plug; and an external cable connected to the PCB and extending through the sealing grommet and through the encapsulant sealing material.Type: GrantFiled: June 2, 2022Date of Patent: May 23, 2023Assignee: Parker-Hannifin CorporationInventors: Steve A. Robison, Anand Hariharan, Kayon W. Chin, Richard J. Evans
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Publication number: 20230061380Abstract: An example sensor includes a PCB mounted in an internal chamber of housing, wherein the PCB comprises calibration electrical contact points; a sealing grommet mounted in the internal chamber, wherein the sealing grommet comprises an axial hole aligned with the calibration electrical contact points, thereby providing access to the calibration electrical contact points of the PCB; a grommet plug disposed in the axial hole of the sealing grommet; a sensing element disposed in the housing and electrically-coupled to the PCB via an electrical connection; an encapsulant sealing material deposited on the sealing grommet and the grommet plug; and an external cable connected to the PCB and extending through the sealing grommet and through the encapsulant sealing material.Type: ApplicationFiled: June 2, 2022Publication date: March 2, 2023Inventors: Steve A. Robison, Anand Hariharan, Kayon W. Chin, Richard J. Evans
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Patent number: 7352214Abstract: A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.Type: GrantFiled: February 16, 2005Date of Patent: April 1, 2008Assignee: Broadcom CorporationInventors: Richard J. Evans, Martin G. Vickers, Simon T. Smith
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Patent number: 7139789Abstract: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.Type: GrantFiled: September 23, 2002Date of Patent: November 21, 2006Assignee: Broadcom CorporationInventor: Richard J. Evans
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Patent number: 6966017Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.Type: GrantFiled: June 18, 2002Date of Patent: November 15, 2005Assignee: Broadcom CorporationInventor: Richard J. Evans
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Publication number: 20030061253Abstract: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.Type: ApplicationFiled: September 23, 2002Publication date: March 27, 2003Applicant: Broadcom CorporationInventor: Richard J. Evans
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Publication number: 20030051197Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.Type: ApplicationFiled: June 18, 2002Publication date: March 13, 2003Applicant: Broadcom CorporationInventor: Richard J. Evans
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Publication number: 20030009714Abstract: The invention provides apparatus and a method of scan testing digital logic circuits, in particular faults in circuit operation during operational transitions in the circuit. The system is intended for use in testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; system disabling the external clock, synchronising testing means with the internal oscillating means, performing testing on the circuit while the external clock is disabled and re-enabling the external clock following testing. In the preferred embodiment, the test clock is synchronised with a PLL. The preferred embodiments address the difficulties with the conventional test methodology by synchronising the test clock with the phase locked loop internal to the IC.Type: ApplicationFiled: June 18, 2002Publication date: January 9, 2003Applicant: Broadcom CorporationInventor: Richard J. Evans
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Patent number: 6425092Abstract: Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.Type: GrantFiled: June 17, 1998Date of Patent: July 23, 2002Assignee: International Business Machines CorporationInventors: Richard J. Evans, Scott W. Gould, Anthony M. Palagonia, Sebastian T. Ventrone
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Patent number: 6050326Abstract: A heat dissipation apparatus for cooling one or more electronic devices. The apparatus utilizes a moving heat sink a portion of which is in contact with the device to be cooled. The moving heat sink may be in the form of a rotating disk, moving belt or strip. The heat sink may be made from various materials such as metals or plastics.Type: GrantFiled: May 12, 1998Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: Richard J. Evans, David L. Gardell, Anthony M. Palagonia
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Patent number: 6010392Abstract: A fixture for holding a semiconductor die against an abrasive media for the purpose of thinning the die is described. The fixture provides means for aligning the back of the die to a reference plane that is coplanar with the plane of the abrasive and is in contact with the abrasive media during the thinning process.Type: GrantFiled: February 17, 1998Date of Patent: January 4, 2000Assignee: International Business Machines CorporationInventors: Richard J. Evans, Philip S. Phoenix, David P. Vallett
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Patent number: 5905670Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.Type: GrantFiled: May 13, 1997Date of Patent: May 18, 1999Assignee: International Business Machines Corp.Inventors: Gordon M. Babson, Allen W. Brouillette, Richard J. Evans, Robert J. Finch, Philip H. Noel, Richard J. Ross
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Patent number: 5847988Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.Type: GrantFiled: January 13, 1998Date of Patent: December 8, 1998Assignee: International Business Machines CorporationInventors: Gordon M. Babson, Allen W. Brouillette, Richard J. Evans, Robert J. Finch, Philip H. Noel, Richard J. Ross
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Patent number: 4159219Abstract: An unbacked decorative thermoplastic vinyl resin containing surface covering having a self-induced tension is manufactured by (1) fusing a vinyl resin composition decorative layer and a vinyl resin composition backing layer to a strippable dimensionally stable backing to form a fused thermoplastic decorative surface covering, and (2) removing the strippable backing and rolling the surface covering, thus placing the surface covering under tension and thereby elongating the outward facing layer and compressing the other layer. The composition and structure of the outward facing layer is such that, on unrolling the surface covering, the elongated layer overcomes the compressed layer and the surface covering is stretched to a dimension greater than its original unrolled dimension. On securing the surface covering at its periphery only, the tendency of the surface covering to return to its original dimension, i.e. its elastic memory, creates a self-induced tension therein.Type: GrantFiled: December 12, 1977Date of Patent: June 26, 1979Assignee: Armstrong Cork CompanyInventor: Richard J. Evans
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Patent number: 4135675Abstract: A flooring product is made on a paper carrier and the paper carrier is removed from the flooring just prior to the time the flooring is rolled up. The paper carrier, which is free from the flooring, is wrapped up with the roll of flooring to prevent adhesion between the flooring surfaces in the roll and to provide some physical stability to the roll of flooring when it is standing on its end.Type: GrantFiled: June 1, 1977Date of Patent: January 23, 1979Assignee: Armstrong Cork CompanyInventors: William A. Greiner, Jr., Richard J. Evans