Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a repair site. In one embodiment, a repair device includes a plate member and an anchor. The plate member having a periphery, the plate member configured to be positioned along an outer surface of the soft tissue. The anchor includes a base and six legs extending from the base, the six legs extending from the base being moveable to a curled configuration such that the six legs wrap around separate portions of the periphery of the plate member with the soft tissue therebetween. In this manner, the repair device may be anchored to the soft tissue.

Abstract: Devices, systems and/or methods for repairing soft tissue adjacent a soft tissue repair site. In one embodiment, a repair device configured to couple to soft tissue is provided. The repair device includes a capture portion and an anchor portion. The capture portion configured to extend with radial portions. The anchor portion includes a base with multiple legs extending therefrom. The multiple legs are configured to move from a linear position to a formed position such that, in the formed position, the multiple legs couple to structure of the capture portion.

Abstract: An example sensor includes a PCB mounted in an internal chamber of housing, wherein the PCB comprises calibration electrical contact points; a sealing grommet mounted in the internal chamber, wherein the sealing grommet comprises an axial hole aligned with the calibration electrical contact points, thereby providing access to the calibration electrical contact points of the PCB; a grommet plug disposed in the axial hole of the sealing grommet; a sensing element disposed in the housing and electrically-coupled to the PCB via an electrical connection; an encapsulant sealing material deposited on the sealing grommet and the grommet plug; and an external cable connected to the PCB and extending through the sealing grommet and through the encapsulant sealing material.

Abstract: An example sensor includes a PCB mounted in an internal chamber of housing, wherein the PCB comprises calibration electrical contact points; a sealing grommet mounted in the internal chamber, wherein the sealing grommet comprises an axial hole aligned with the calibration electrical contact points, thereby providing access to the calibration electrical contact points of the PCB; a grommet plug disposed in the axial hole of the sealing grommet; a sensing element disposed in the housing and electrically-coupled to the PCB via an electrical connection; an encapsulant sealing material deposited on the sealing grommet and the grommet plug; and an external cable connected to the PCB and extending through the sealing grommet and through the encapsulant sealing material.

Abstract: A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.

Abstract: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.

Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

Abstract: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.

Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

Abstract: The invention provides apparatus and a method of scan testing digital logic circuits, in particular faults in circuit operation during operational transitions in the circuit. The system is intended for use in testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; system disabling the external clock, synchronising testing means with the internal oscillating means, performing testing on the circuit while the external clock is disabled and re-enabling the external clock following testing. In the preferred embodiment, the test clock is synchronised with a PLL. The preferred embodiments address the difficulties with the conventional test methodology by synchronising the test clock with the phase locked loop internal to the IC.

Abstract: Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.

Abstract: A heat dissipation apparatus for cooling one or more electronic devices. The apparatus utilizes a moving heat sink a portion of which is in contact with the device to be cooled. The moving heat sink may be in the form of a rotating disk, moving belt or strip. The heat sink may be made from various materials such as metals or plastics.

Abstract: A fixture for holding a semiconductor die against an abrasive media for the purpose of thinning the die is described. The fixture provides means for aligning the back of the die to a reference plane that is coplanar with the plane of the abrasive and is in contact with the abrasive media during the thinning process.

Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

Abstract: A process and structure are disclosed for a programmable array for use in a read-only memory comprising diode elements and shorted diode elements. The elements are connected across bit and wordlines. The invention utilizes lateral polysilicon diodes and metal silicide layer bridging the junction of pre-selected diodes to short pre-selected diode elements. Programming is accomplished by either forming the silicide layer across the junctions of pre-selected diodes or removing the silicide layer from the junctions of pre-selected diodes.

Abstract: An unbacked decorative thermoplastic vinyl resin containing surface covering having a self-induced tension is manufactured by (1) fusing a vinyl resin composition decorative layer and a vinyl resin composition backing layer to a strippable dimensionally stable backing to form a fused thermoplastic decorative surface covering, and (2) removing the strippable backing and rolling the surface covering, thus placing the surface covering under tension and thereby elongating the outward facing layer and compressing the other layer. The composition and structure of the outward facing layer is such that, on unrolling the surface covering, the elongated layer overcomes the compressed layer and the surface covering is stretched to a dimension greater than its original unrolled dimension. On securing the surface covering at its periphery only, the tendency of the surface covering to return to its original dimension, i.e. its elastic memory, creates a self-induced tension therein.

Abstract: A flooring product is made on a paper carrier and the paper carrier is removed from the flooring just prior to the time the flooring is rolled up. The paper carrier, which is free from the flooring, is wrapped up with the roll of flooring to prevent adhesion between the flooring surfaces in the roll and to provide some physical stability to the roll of flooring when it is standing on its end.

Abstract: A method of surfacing an area with a surface covering having a decorative wear layer formed of a thermoplastic vinyl resin-containing composition that has been formed by fusing under heat and/or pressure and bonded to a strippable backing before stresses, set up therein during formation, are relieved. The backing is removed prior to installation and the wear layer secured at its perimeter only against movement with respect to the surface being covered and before stresses therein are relieved.