Patents by Inventor Richard J. Ferrant

Richard J. Ferrant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7020016
    Abstract: A data value is stored in a random access memory cell by driving the bit lines of the cell to complementary values representative of the value. The word line for the cell is driven to make a cell selection and cause the data value to be loaded into the cell from the bit lines. Thereafter, the word line is deselected. Following deselection, both bit lines are discharged to a logic low level. During discharging, however, a leakage current is allowed to flow through at least one of the bit lines so that the memory cell maintains the stored data value.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: March 28, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Richard J. Ferrant, Tsin C. Chan
  • Patent number: 6808990
    Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 26, 2004
    Assignee: STMicroelectronics, Inc.
    Inventors: Richard J. Ferrant, Tsiu C. Chan
  • Publication number: 20030122172
    Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Richard J. Ferrant, T. C. Chan
  • Patent number: 6583459
    Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: June 24, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Richard J. Ferrant, Tsiu C. Chan
  • Patent number: 6477673
    Abstract: Programmability of the data background patterns used to test random-access-memories (RAMs) is accomplished by adding to the memory input/output (I/O) buffers of RAM memory, for each data bit of a data background pattern to be programmed, a programming mechanism and a selection mechanism. The programming mechanism is capable of programming a data bit of the data background pattern in accordance with a programming information signal provided to the RAM. The selection mechanism provides either the programmed data bit or a normal, application data bit to an input/output buffer of the RAM in accordance with whether the RAM is in a test mode or a normal operating mode, as indicated by a test control signal provided to the RAM.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: November 5, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Richard J. Ferrant, Robert Alan Wadsworth
  • Patent number: 6005818
    Abstract: A dynamic access memory (DRAM) device includes a plurality of memory cells for storing data signals. The DRAM device has a row decoding mechanism that allows selected memory cells to be accessed upon receipt of a row address signal during a read operation and a write operation. A latching mechanism is provided and receives and holds onto the data signals from the selected memory cells when activated during the read operation and also isolates itself from the selected memory cells when deactivated during the write operation. An included refresh address generating mechanism generates a plurality of internal row address signals that allows selection of a plurality of memory cells for refreshing the stored data signals. The DRAM device also has a multiplexer mechanism that transmits a plurality of external row address signals to the row decoding mechanism in the write operation.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: December 21, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard J. Ferrant
  • Patent number: 5973985
    Abstract: Disclosed is a multiport SRAM cell. The cell state may be switched by controlling the potential on a single bit line only. A true dual port SRAM cell (in which the two ports may be accessed nearly simultaneously without needing peripheral arbitration logic) employs two cross-coupled inverters, two bit lines, two word lines, and two access transistors. The SRAM cells employ internal "pseudo inverters" that can be independently powered on and off. By powering one of them off during the write operation, the internal conflict associated with changing the value of a stored bit is avoided. Each pseudo inverter may be powered on and off via a pseudo ground or a pseudo Vdd line which controls the potential to locations where ground or Vdd are normally supplied to CMOS inverters.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard J. Ferrant