Abstract: A CMOS Reed-Solomon decoding circuit calculates syndromes, executes a Berlekamp algorithm, performs a Chien Search, and corrects a delayed version of the received data according to a calculated magnitude of error. The circuit is optimized in terms of chip territory and circuit complexity. Signals are provided to indicate uncorrectable packet errors and other transmission errors.

Abstract: A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Abstract: An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.

Abstract: A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Abstract: An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.

Abstract: A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).

Abstract: A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the i

Abstract: A method of comparing a first multibit digital signal with a second multibit digital signal wherein to increase speed of obtaining an output signal said method comprises inputting input signals for each of said first and second signals and forming a respective codeword for each input signal, each codeword being at least one bit longer than the respective input signal and formed by the same error correcting code for both signals to provide increased minimum Hamming distance for the respective codewords, comparing respective bit locations of the codewords to form a plurality of match indicating signals for respective bit locations thereby indicating any mismatch by a mismatch at at least two bit locations, supplying said match indicating signals in parallel to gating circuitry arranged to provide an output indicating a match or mismatch between said codewords, said output being provided with a time delay less than that required for a single bit mismatch.