Patents by Inventor Richard J. Greco

Richard J. Greco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10223171
    Abstract: Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Stephanie Labasan, Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco
  • Patent number: 10146287
    Abstract: Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Federico Ardanaz, Ian M. Steiner, Jonathan M. Eastep, Richard J. Greco, Krishnakanth V. Sistla, Micah Barany, Andrew J. Herdrich
  • Patent number: 10101786
    Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Jonathan M. Eastep, Richard J. Greco
  • Patent number: 10048736
    Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Jonathan M. Eastep, Richard J. Greco
  • Publication number: 20180067533
    Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.
    Type: Application
    Filed: August 29, 2017
    Publication date: March 8, 2018
    Applicant: INTEL CORPORATION
    Inventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
  • Publication number: 20180059768
    Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.
    Type: Application
    Filed: October 19, 2017
    Publication date: March 1, 2018
    Applicant: INTEL CORPORATION
    Inventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
  • Publication number: 20170357580
    Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
    Type: Application
    Filed: June 21, 2017
    Publication date: December 14, 2017
    Inventors: Avinash Sodani, Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Milind B. Girkar, Christopher M. Cantalupo
  • Patent number: 9829902
    Abstract: Apparatus, systems, and methods provide dynamic power steering that includes determining a sequence of phases of an application in a node. The sequence corresponds to a time interval associated with an energy budget. For each phase, the dynamic power steering includes determining a power scaling comprising a measured response to an increase or decrease in power distributed to a plurality of power domains in the node, and based on the power scaling for each phase, determining a temporal power distribution between the phases in the sequence to satisfy the energy budget.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 28, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco
  • Patent number: 9811143
    Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
  • Publication number: 20170285710
    Abstract: Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Federico Ardanaz, Ian M. Steiner, Jonathan M. Eastep, Richard J. Greco, Krishnakanth V. Sistla, Micah Barany, Andrew J. Herdrich
  • Publication number: 20170277576
    Abstract: Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Applicant: Intel Corporation
    Inventors: Stephanie Labasan, Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco
  • Patent number: 9753526
    Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
  • Patent number: 9720827
    Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Avinash Sodani, Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Milind B. Girkar, Christopher M. Cantalupo
  • Publication number: 20170187579
    Abstract: Systems, apparatuses and methods may provide for a smart power manager that dynamically activates or deactivates the individual lanes of each link of a router based on the allocated power limit and the connected applications. The smart power manager may optimize the router throughput for a given power limit dictated by a global power manager, and use a fine grained credit mechanism to track active lanes. The router power manager may also adjust the number of active lanes for each link individually so that highly utilized links will have more active lanes than links that are idle.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Eric R. Borch, Jonathan M. Eastep, Richard J. Greco
  • Patent number: 9477533
    Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Rob F. Van Der Wijngaart, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Publication number: 20160188380
    Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Rob F. Van Der Wijngaart, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Publication number: 20160187944
    Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Inventors: Jonathan M. Eastep, Ilya Sharapov, Richard J. Greco, Steve S. Sylvester, David N. Lombard
  • Publication number: 20160179162
    Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: JONATHAN M. EASTEP, RICHARD J. GRECO
  • Publication number: 20160179117
    Abstract: Apparatus, systems, and methods provide dynamic power steering that includes determining a sequence of phases of an application in a node. The sequence corresponds to a time interval associated with an energy budget. For each phase, the dynamic power steering includes determining a power scaling comprising a measured response to an increase or decrease in power distributed to a plurality of power domains in the node, and based on the power scaling for each phase, determining a temporal power distribution between the phases in the sequence to satisfy the energy budget.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: JONATHAN M. EASTEP, ROHIT BANERJEE, RICHARD J. GRECO
  • Publication number: 20160179157
    Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: FEDERICO ARDANAZ, JONATHAN M. EASTEP, RICHARD J. GRECO, RAMKUMAR NAGAPPAN, ALAN B. KYKER