Abstract: An integrated circuit and a method of altering such an integrated circuit (e.g., during final testing of the circuit) are such that the method can be used to program a circuit, wire around defective portions of a circuit, or otherwise permanently alter a circuit by employing a directed energy source such as a laser to sever electrical paths in an upper layer of metallization in an integrated circuit. The integrated circuit comprises a laminated upper metallization layer, the upper layer(s) of which laminate are removed from the laser-alterable lower layer at selected locations in the metallization layer to provide laser-alteration sites in the circuit. In a preferred embodiment, the upper metallization layer comprises a two-layer laminate including an upper, relatively thick layer of an aluminum/silicon alloy and a lower, relatively thin layer of titanium nitride.

Abstract: A chip having field effect transistors which have differing threshold voltages determined in a single masking step and a method of making the chip provides a chip usable at both cryogenic and room temperatures without a costly additionaly masking step. The chip has devices with low threshold voltages that are therefore optimized for performance at low temperatures, and devices with high threshold voltages that are optimized for performance at higher temperatures. Such high threshold voltage devices are also usable, though sub-optimally, at lower temeperatures such as cryogenic temperatures. The two sets of devices have their threshold voltages determined in a single masking step, with the higher threshold voltage values being provided during this step by reducing the width of a device to produce a parasitic effect.

Abstract: An integrated circuit and a method of altering such an integrated circuit (e.g., during final testing of the circuit) are disclosed. The method can be used to program a circuit, wire around defective portions of a circuit, or otherwise permanently alter a circuit by employing a directed energy source such as a laser to sever electrical paths in an upper layer of metallization in an integrated circuit. The integrated circuit comprises a laminated upper metallization layer, the upper layer(s) of which laminate are removed from the laser-alterable lower layer at selected locations in the metallization layer to provide laser-alteration sites in the circuit. In a preferred embodiment, the upper metallization layer comprises a two-layer laminate including an upper, relatively thick layer of an aluminum/silicon alloy and a lower, relatively thin layer of titanium nitride.

Abstract: The sense circuit includes two "skewed" inverters. The inverters are skewed in that their switching point is set closer to one (e.g. V.sub.HIGH) of the inverter operating potentials than to the other potential (e.g. V.sub.LOW). Therefore, the skewed inverters respond earlier to signals making a transition from a first level to a second level than to signals, of like slope, making a transition from the second to the first level. Each inverter is connected at its input to a different one of first and second bit lines and the output of each inverter is connected to the input of the other via a gating transistor whose conductivity is controlled by the output of the other inverter. Skewing the inverters enables sequential operation of the inverters of the circuit.

Abstract: A unidirectional conducting element is series connected between an input terminal and the source electrode of an insulated-gate field-effect transistor (IGFET) having an electrically floating substrate. The unidirectional conducting element is poled to conduct in a direction which is opposite to the forward direction of the source-to-substrate junction in order to isolate the substrate of the IGFET and its associated capacitance from a signal source connected to the input terminal. The invention is particularly useful in high density, high speed, random access memories (RAMs) to prevent the loading of bit lines by non-selected memory cells.

Abstract: The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the base of a bipolar transistor to provide both bipolar current handling capability and bipolar radiation hardness while retaining MNOS memory performance.

Abstract: The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the emitter of a bipolar transistor to provide both bipolar collector-to-emitter breakdown voltage capability and bipolar radiation hardness while retaining MNOS memory performance.

Abstract: A bias generator produces a voltage (V.sub.R) which is applied to the control electrode of a gating transistor via whose conduction path the contents of a memory cell are read-out. V.sub.R is such that, during read-out, the maximum amplitude of the gate-to-source potential (V.sub.GS) applied to the gating transistor, in a direction to turn it on, is approximately equal to a fraction of the memory cell supply voltage plus an offset voltage comparable to the threshold voltage (V.sub.T) of the gating transistor. The bias generator includes a voltage divider connected across the same supply voltage source as the memory cell. A portion of the supply voltage (K V.sub.DD) generated at a node of the divider is applied to an offset voltage generating circuit which includes as least one device of the same type as the gating transistor and which produces V.sub.R at its output. V.sub.R is approximately equal to K V.sub.DD offset by a voltage comparable to the V.sub.T of the gating transistor. Applying V.sub.