Abstract: A method and system is provided for detecting, commanding and controlling diverse home devices currently connected to a home network. An interface is provided for accessing the home devices that are currently connected to a home network. According to the method, a device link file is generated, wherein the device link file identifies home devices that are currently connected to the home network. A device link page is created, wherein the device link page contains a device button that is associated with each home device that is identified in the device link file. A hyper-text link is associated with each device button, wherein the hyper-text link provides a link to an HTML page that is contained on the home device that is associated with the device button, and the device link page is displayed on a browser based home device.

Abstract: A switching circuit is described, for selecting between first and second clock signals. When it is desired to switch from the first to the second clock signal, the first clock signal is de-selected in synchronism with the beat of the first clock and then, after a delay, the second clock signal is selected in synchronism with the beat of the second clock. Conversely, when it is desired to switch from the second to the first clock signal, the second clock signal is de-selected in synchronism with the beat of the second clock and then, after a delay, the first clock signal is selected in synchronism with the beat of the first clock. This avoids the possibility of a short pulse or "glitch" at the instant of switch-over.

Abstract: A parallel-to-serial converter is described, comprising a shift register into which a data word can be loaded in parallel and then shifted out serially. As the data is shifted out, a string of zeros is shifted in. When a predetermined number of zeros is detected, a flip-flop is set at the next clock beat. This switches the shift register into its parallel load mode so that, at the next again clock beat the shift register is parallel loaded with the next data word. The detection of the predetermined number of zeros and the setting up of the shift register occur in different clock periods, allowing the clock period to be reduced, thus increasing the speed of operation.

Abstract: In order to synchronize data signals transferred from a source unit to a destination unit, a clock signal is transmitted from the destination unit to the source unit and transmission of data is effected under control of the received clock signal. The received clock signal is retransmitted back to the destination unit with the trasmitted data and is used to register receipt of the data.