Abstract: Systems are provided having, for example, at least first and second processing units, an optical bus system coupled to the at least first and second processing units, and an optical bus controller coupled to the optical bus system. The optical bus system includes a plurality of optical switches and each optical switch includes, for example, at least a first switch state for directing light in at least a first direction and a second switch state for directing light in at least a second direction. Methods for optical bus communication are also provided.

Abstract: A circuit board assembly having a circuit board and a column grid array (“CGA”) integrated circuit package. The CGA package has a substrate having an array of solder columns extending from a bottom surface. A frame surrounds the CGA integrated circuit package and is affixed thereto. The frame extends from the substrate to a portion of the circuit board when the column grid array integrated circuit package is mounted on the circuit board to support the column grid array integrated circuit package. The frame is affixed to the CGA integrated circuit package by adhesive after the CGA integrated circuit package is mounted on the circuit board, the adhesive accommodating any variations in height of the CGA integrated circuit package.

Abstract: A temperature-controlled rework system comprises a manifold assembly adapted to direct a cooling gas flow toward an area of a printed circuit board adjacent a rework zone to reduce a temperature of the adjacent area to below a temperature of the rework zone. The system also comprises a temperature control system adapted to monitor the temperature of the adjacent area.

Abstract: A temperature-controlled rework system comprises a manifold assembly adapted to direct a cooling gas flow toward an area of a printed circuit board adjacent a rework zone to reduce a temperature of the adjacent area to below a temperature of the rework zone. The system also comprises a temperature control system adapted to monitor the temperature of the adjacent area.

Abstract: A rework nozzle comprises a rework duct adapted to direct a high temperature gas flow toward a rework component. The rework nozzle also comprises at least one cooling duct adapted to direct a low temperature gas flow to an area adjacent the component to maintain the adjacent area at a reduced temperature relative to a temperature of the high temperature gas flow.

Abstract: A circuit board assembly having a circuit board and a column grid array (“CGA”) integrated circuit package. The CGA package has a substrate having an array of solder columns extending from a bottom surface. A frame surrounds the CGA integrated circuit package and is affixed thereto. The frame extends from the substrate to a portion of the circuit board when the column grid array integrated circuit package is mounted on the circuit board to support the column grid array integrated circuit package. The frame is affixed to the CGA integrated circuit package by adhesive after the CGA integrated circuit package is mounted on the circuit board, the adhesive accommodating any variations in height of the CGA integrated circuit package.

Abstract: A circuit board assembly having a circuit board and a column grid array (“CGA”) integrated circuit package. The CGA package has a substrate having an array of solder columns extending from a bottom surface. A frame surrounds the CGA integrated circuit package and is affixed thereto. The frame extends from the substrate to a portion of the circuit board when the column grid array integrated circuit package is mounted on the circuit board to support the column grid array integrated circuit package. The frame is affixed to the CGA integrated circuit package by adhesive after the CGA integrated circuit package is mounted on the circuit board, the adhesive accommodating any variations in height of the CGA integrated circuit package.

Abstract: A circuit board assembly having a circuit board and a column grid array (“CGA”) integrated circuit package. The CGA package has a substrate having an array of solder columns extending from a bottom surface. A frame surrounds the CGA integrated circuit package and is affixed thereto. The frame extends from the substrate to a portion of the circuit board when the column grid array integrated circuit package is mounted on the circuit board to support the column grid array integrated circuit package. The frame is affixed to the CGA integrated circuit package by adhesive after the CGA integrated circuit package is mounted on the circuit board, the adhesive accommodating any variations in height of the CGA integrated circuit package.

Abstract: An integrated circuit device package in accordance with the invention comprises a first land grid array (LGA) interposer socket positioned between, and in communication with, an LGA integrated circuit device and a first side of a first circuit board; a second LGA interposer socket positioned between, and in communication with, a second circuit board and a second side of the first circuit board, wherein the second side of the first circuit board is opposite to and parallel with the first side of the first circuit board; and a clamping mechanism for compressively urging together the LGA integrated circuit device, the first LGA interposer socket, the first circuit board, the second LGA interposer socket, and the second circuit board into electrical interconnection under a predetermined load.

Abstract: A low skew clocking system for VLSI intergrated circuits in which a reference chip, preferably a microprocessor, generates local synchronization signals for the other chips on a common PC board. This reduces the clock skew between the reference chip and all other chips by as much as 50%. Skew between chips is further reduced by using a differential MOS driver responsive to locally generated synchronization signals to generate differential synchronization outputs. Processing speed may be further improved in accordance with the invention by implementing a quadrature clocking scheme using the differential synchronization outputs from the MOS driver whereby the timing delays between the differential quadrature clocking signals are determined by the PC board delays.

Abstract: A circuit which performs a hashing (exclusive OR) function and has a high drive output for driving large capacitive loads. The invention incorporates a hashing function into an output driver, such as address driver, by incorporating a pull-down circuit into the output driver which is responsive to the respective inputs to be hashed together. A very short setup time for the inputs and a very fast evaluation of the hashing function is made possible in accordance with the invention by precharging the pull-down circuit before the inputs are received. The pull-down circuit is arranged such that a high output is outputted only when both of the input signals in a discharge path are of the same logic level. The resulting system is not limited by slow evaluation of the hashing function and thus has improved performance.