Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

Abstract: Circuit element having a first layer composed of an electrically insulating substrate material, a first electrically conductive material which is in the form of at least one discrete area, such that it is embedded in or applied to the substrate material, a second layer having a second electrically conductive material, and a monomolecular layer, which is composed of electrically active molecules which transports charge carriers, arranged between the first layer and the second layer. The monomolecular layer is immobilized and makes electrical contact with the second layer. Each of the electrically active molecules has a first unit, which is used as an electron donor, a second unit, which is used as an electron acceptor, wherein the electron donor and the electron acceptor form a diode, and at least one redox-active unit, by means of which a variable resistance is formed, arranged between the first unit and the second unit.

Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.