Abstract: A carrier for an integrated chip is embedded into a substrate, so that stresses due to thermal expansion are uniformly distributed over an interface between the substrate and the carrier (hereinafter “embedded carrier”). Such an embedded carrier may be formed of a material having a coefficient of thermal expansion similar or identical to the coefficient of thermal expansion of an integrated circuit chip to be mounted thereon, so as to eliminate stresses (due to thermal expansion) at joints between the carrier and the integrated circuit chip. The just-described joints may be formed by any method well known in the art, e.g. flip-chip bonding. Such packaging of one or more integrated circuit chip(s) eliminates reliability issues associated with conventional flip chip bonded components, which are caused by, for example, concentration of stresses in conventional solder ball interconnections between a chip and a substrate.

Abstract: An integrated circuit package includes at least one semiconductor die embedded in a substrate made of a heat deformable material such as plastic or a combination of plastics. The at least one die is embedded so that the top surface of the at least one die, which contains a plurality of bonding pads, is exposed, and, in certain embodiments, substantially coplanar with the top surface of the substrate. A layer of conductive material is then formed on the top surface of the substrate and on the top surfaces(s) of at least one semiconductor die. This layer is formed into a plurality of electrically conductive paths each path beginning at a selected bonding pad and terminating in an electrically conductive land on the top surface of the substrate.

Abstract: A monolithic integrated structure including one or more packaged components such as integrated circuits, discreet components, LED's, photocouplers and the like is formed by placing electrically conductive lands on one surface of each packaged component, and then placing one or more packaged components into a substrate such that the surface of each packaged component containing the electrically conductive lands is visible and substantially coplanar with the top surface of the substrate. An electrically conductive layer is then formed over the top surface of the substrate, on the visible surfaces of each of the packaged components and on the electrically conductive lands contained thereon. The electrically conductive layer is then patterned using standard photolithographic techniques known in the semiconductor and printed circuit processing arts to form an electrical interconnect which connects the packaged components into a desired electrical circuit.

Abstract: A monolithic integrated structure including one or more packaged components such as integrated circuits, discreet components, LED's, photocouplers and the like is formed by placing electrically conductive lands on one surface of each packaged component, and then placing one or more packaged components into a substrate such that the surface of each packaged component containing the electrically conductive lands is visible and substantially coplanar with the top surface of the substrate. An electrically conductive layer is then formed over the top surface of the substrate, on the visible surfaces of each of the packaged components and on the electrically conductive lands contained thereon. The electrically conductive layer is then patterned using standard photolithographic techniques known in the semiconductor and printed circuit processing arts to form an electrical interconnect which connects the packaged components into a desired electrical circuit.

Abstract: One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system.

Abstract: One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system.

Abstract: One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system.

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for interconnecting the terminals of electronic components mounted on printed circuit boards (PCBs), multichip modules (MCMs) or in integrated circuit packages (IC packages). Both types of programmable elements can be fabricated as part of the regular processes used to fabricate PCBs, MCMs, or IC package (pin grid array). For fuses and antifuses, the material, geometry and dimensions can be varied to minimize the real estate and maximize programming efficiency (reduce programming time). Each type of programmable element, fuse or antifuse, can be separately used in matrices to form programmable board and package substrates. When both types of programmable elements are used together, more efficient placement and route architectures take advantage of the characteristics of each type of programmable element. Furthermore, combinations of both fuses and antifuses in the same structure allows the architecture to be reprogrammable.

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable cable in one embodiment and a cable adapter in another embodiment. The cable and the cable adapter can be used for interconnecting a cable connector of a first configuration to a cable connector of a second configuration.

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable burn-in board in one embodiment and an electrically programmable device-under-test (DUT) card in another embodiment. Both types of programmable elements can also be used in a reconfiguration device for interconnecting electrical contacts in a first configuration to electrical contacts in a second configuration. The various embodiments of this invention include, for example, a component socket, a socket adapter, a cable, a cable adapter, a scrambler card for a burn-in board and a device-under-test card for a burn-in board. A method for forming a fuse is also disclosed.

Abstract: A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.

Abstract: A programming method in accordance with this invention partitions traces of a fuse matrix into groups wherein each group contains traces connected to fuses that are to remain intact. All of the traces in a group are connected to a first voltage so that the fuses between traces in the group are subjected to minimal currents. In one embodiment, all of the traces that are not in the group connected to the first voltage are connected to a second voltage such that a programming current passes through fuses to be programmed. In an alternative embodiment, traces in a second group are connected to the second voltage and all of the remaining traces are shorted to each other.