Patents by Inventor Richard J. Saia
Richard J. Saia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7158383Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.Type: GrantFiled: November 18, 2003Date of Patent: January 2, 2007Assignee: General Electric CompanyInventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
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Patent number: 7011983Abstract: Large, light-weight organic devices and methods of preparing large, light-weight organic devices. Specifically, flexible and rigid light-weight plastics are implemented. The flexible plastic may be disposed from a reel. A metal grid is fabricated on the flexible plastic to provide current conduction over the large area. A transparent oxide layer is provided over the metal grid to form the bottom electrode of the organic device. A light emitting or light gathering organic layer is disposed on the transparent oxide layer. A second electrode is disposed over the organic layer. Electrodes are coupled to the metal grid and the second electrode to provide electrical current to or from the organic layer. Depending on the type of materials used for the organic layer, the organic device may comprise an area light device or a photovoltaic device.Type: GrantFiled: December 20, 2002Date of Patent: March 14, 2006Assignee: General Electric CompanyInventors: Donald F. Foust, Anil R. Duggal, Richard J. Saia, Herbert S. Cole
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Patent number: 6790779Abstract: A method for creating deep features in a Si-containing substrate for use in fabricating MEMS type devices is provided. The method includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.Type: GrantFiled: July 24, 2002Date of Patent: September 14, 2004Assignee: Lockheed Martin CorporationInventors: James H. Schermerhorn, Matthew C. Nielsen, Richard J. Saia, Jeffrey B. Fortin
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Publication number: 20040121508Abstract: Large, light-weight organic devices and methods of preparing large, light-weight organic devices. Specifically, flexible and rigid light-weight plastics are implemented. The flexible plastic may be disposed from a reel. A metal grid is fabricated on the flexible plastic to provide current conduction over the large area. A transparent oxide layer is provided over the metal grid to form the bottom electrode of the organic device. A light emitting or light gathering organic layer is disposed on the transparent oxide layer. A second electrode is disposed over the organic layer. Electrodes are coupled to the metal grid and the second electrode to provide electrical current to or from the organic layer. Depending on the type of materials used for the organic layer, the organic device may comprise an area light device or a photovoltaic device.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Donald F. Foust, Anil R. Duggal, Richard J. Saia, Herbert S. Cole
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Publication number: 20040114336Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.Type: ApplicationFiled: November 18, 2003Publication date: June 17, 2004Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
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Publication number: 20040063294Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
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Patent number: 6709944Abstract: A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.Type: GrantFiled: September 30, 2002Date of Patent: March 23, 2004Assignee: General Electric CompanyInventors: Kevin M. Durocher, Richard J. Saia, Vikram B. Krishnamurthy
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Publication number: 20040018734Abstract: A method for creating deep features in a Si-containing substrate for use in fabricating MEMS type devices is provided. The method includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.Type: ApplicationFiled: July 24, 2002Publication date: January 29, 2004Applicant: LOCKHEED MARTIN CORPORATIONInventors: James H. Schermerhorn, Matthew C. Nielsen, Richard J. Saia, Jeffrey B. Fortin
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Patent number: 5950303Abstract: A substrate stack is suspended within a stack holder to position upper and lower stack surfaces coplanar with upper and lower holder surfaces. Laminating heat and pressure is simultaneously applied to the upper and lower surfaces to laminate a carrier interconnect film to top and bottom stack portions simultaneously. Subsequent wet chemical processing of both stack edges may also be simultaneous to effect savings in manufacturing costs.Type: GrantFiled: April 3, 1998Date of Patent: September 14, 1999Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Paul A. McConnelee, Richard J. Saia, Kevin M. Durocher
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Patent number: 5531018Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.Type: GrantFiled: December 20, 1993Date of Patent: July 2, 1996Assignee: General Electric CompanyInventors: Richard J. Saia, Mario Ghezzo, Bharat S. K. Bagepalli, Kevin M. Durocher
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Patent number: 5524339Abstract: In a method for preserving an air bridge structure on an integrated circuit chip, a protective layer is plasma-deposited over the top and sides of the air bridge. A high density interconnect structure is applied over the chip and protective layer. The protective film provides mechanical strength during the application of the high density interconnect structure to prevent deformation. It also prevents any contamination from intruding under the air bridge. More importantly, the protective film only negligibly impedes the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure.Type: GrantFiled: September 19, 1994Date of Patent: June 11, 1996Assignee: Martin Marietta CorporationInventors: Bernard Gorowitz, Richard J. Saia, Kevin M. Durocher
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Patent number: 5510281Abstract: A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semiconduType: GrantFiled: March 20, 1995Date of Patent: April 23, 1996Assignee: General Electric CompanyInventors: Mario Ghezzo, Tat-Sing P. Chow, James W. Kretchmer, Richard J. Saia, William A. Hennessy
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Patent number: 5475353Abstract: A micromachined electromagnetic switch, including two soft magnets situated in fixed positions above and below a permanent magnet, toggles between two fixed positions by the application of current in an actuator coil for a brief period. The permanent magnet is attached to a micromachined hinge or spring which moves under the action of a net force, thereby opening or closing the switch. Current in the actuator coil changes the relative strength of the magnetic forces due to the soft magnets. In the absence of current in the actuator coil, the switch is kept in the open or closed position by the attractive magnetic force between the permanent magnet and either the upper or lower soft magnet, whereby the stronger force is exercised between the permanent magnet and the nearest soft magnet.Type: GrantFiled: September 30, 1994Date of Patent: December 12, 1995Assignee: General Electric CompanyInventors: Waseem A. Roshen, Mario Ghezzo, Richard J. Saia, William A. Hennessy, Bharat S. Bagepalli
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Patent number: 5472539Abstract: A low temperature batch method for forming and positioning permanent magnets on electromagnetically actuated micro-fabricated components, such as electrical switches employs a first adhesive, such as a Siltem/epoxy blend of an epoxy resin and a siloxane polyimide polymer, to releasably attach a mold layer of Kapton polyimide to a substrate, which may be the movable portion of a micromechanical structure, or a precursor to such movable portion. A well-shape cavity is formed in the mold layer, and filled with a slurry of rare earth NdFeB magnetic particles suspended in a second adhesive, which is cured to form the body of a magnet. The second adhesive is an SPI/epoxy blend, also of an epoxy resin and a siloxane polyimide polymer, but with a greater adhesion strength and a higher temperature softening point compared to the Siltem/epoxy blend. The entire structure is heated, and the mold layer is pulled off the substrate, while the body of magnetic material remains firmly attached.Type: GrantFiled: June 6, 1994Date of Patent: December 5, 1995Assignee: General Electric CompanyInventors: Richard J. Saia, Kevin M. Durocher, Thomas B. Gorczyca, Mario Ghezzo
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Patent number: 5454904Abstract: Micromachining methods for fabricating micromechanical structures which include plunger elements free to reciprocate within cavities are fabricated using processing steps in common with those employed in high density interconnect (HDI) technology for multi-chip module packaging. A polymer, such as a polyimide, is utilized as a micromachinable material. In one embodiment, cavities are formed in the polymer material by laser ablation, employing a sacrificial layer as a mask. Electroplated copper may be employed as a sacrificial release layer. One particular structure is a micromechanical electric switch including an array of individual switch contacts actuatable in common.Type: GrantFiled: August 5, 1994Date of Patent: October 3, 1995Assignee: General Electric CompanyInventors: Mario Ghezzo, Richard J. Saia, Bharat S. Bagepalli, Imdad Imam, Dennis L. Polla
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Patent number: 5430597Abstract: A circuit interruption device having a plurality of micromechanical switches mounted on a substrate in a parallel-series array. The array includes a plurality of line branches connected in parallel in a circuit line. Each of the line branches has at least two of the switches serially connected therein. The micromechanical switches each has a pair of contacts formed on the substrate, a bridging contact movably formed on the substrate, and an actuator for causing the bridging contact to move in and out of contact with the contacts. The bridging contact can be either a member slidably disposed in a channel formed on the substrate or member attached to an end of a cantilever having its other end attached to the substrate. The actuator is controlled by a trip device which is also mounted on the substrate. The trip device senses the current in the circuit line and causes the switches to open when a predetermined level of current in the line is exceeded.Type: GrantFiled: January 4, 1993Date of Patent: July 4, 1995Assignee: General Electric CompanyInventors: Bharat S. Bagepalli, Mario Ghezzo, Richard J. Saia, Imdad Imam
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Patent number: 5401668Abstract: A method of fabricating a radiation imager with strong structural integrity and adhesion between the scintillator and photosensor array includes the steps of forming a photosensor array on a substrate; depositing a barrier layer over the photosensor array, the barrier layer having an upper surface of silicon nitride; treating the silicon nitride upper surface of the barrier layer to prepare the surface for the deposition of material thereover; and depositing a scintillator material over the treated upper surface of the barrier layer. The silicon nitride upper surface of the barrier layer is typically treated by etching the surface, such as in a reactive ion etch, for a selected amount of time, with less than about 500 .ANG. of material being removed from the surface.Type: GrantFiled: September 2, 1993Date of Patent: March 28, 1995Assignee: General Electric CompanyInventors: Robert F. Kwasnick, Roger S. Ehle, Richard J. Saia
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Patent number: 5374792Abstract: Micromachining methods for fabricating micromechanical structures which include plunger elements free to reciprocate within cavities are fabricated using processing steps in common with those employed in high density interconnect (HDI) technology for multi-chip module packaging. A polymer, such as a polyimide, is utilized as a micromachinable material. In one embodiment, cavities are formed in the polymer material by laser ablation, employing a sacrificial layer as a mask. Electroplated copper may be employed as a sacrificial release layer. One particular structure is a micromechanical electric switch including an array of individual switch contacts actuatable in common.Type: GrantFiled: January 4, 1993Date of Patent: December 20, 1994Assignee: General Electric CompanyInventors: Mario Ghezzo, Richard J. Saia, Bharat S. Bagepalli, Imdad Imam, Dennis L. Polla
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Patent number: 5370972Abstract: Solid state photodetectors having amorphous silicon photodiode bodies with sloped sidewalls allowing for deposition of high integrity conformal layers thereover are produced by etching the amorphous silicon in a mostly anisotropic etchant in a reactive ion etcher in which the pressure of the etchant is controlled. A photoresist mask having sloped sidewalls is formed over the amorphous silicon to be etched and the pressure of the etchant is selected to produce the desired slope of the sidewall in the photodetector body; at lower pressures a smaller slope is produced in the silicon and at higher pressures a steeper slope is produced in the silicon.Type: GrantFiled: September 24, 1992Date of Patent: December 6, 1994Assignee: General Electric CompanyInventors: Richard J. Saia, Robert F. Kwasnick, Brian W. Giambattista
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Patent number: 5367585Abstract: A microelectromechanical photonic switch includes first and second waveguides. Insulative cladding containing a gap and having a lower refractive index than the refractive indices of the first and second waveguides is situated between the first and second waveguides. One electrode comprising an at least partially transparent material is situated on the same side of the gap as the second waveguide. An additional electrode is provided either on the same side of the gap as the first waveguide or over a piezoelectric strip above a cladding layer on the second waveguide. At least one of the electrodes is capable of being advanced towards the other of the electrodes so as to cause one of the first and second waveguides to advance towards the other of the first and second waveguides.Type: GrantFiled: October 27, 1993Date of Patent: November 22, 1994Assignee: General Electric CompanyInventors: Mario Ghezzo, Christopher P. Yakymyshyn, Richard J. Saia, Dennis L. Polla