Patents by Inventor Richard J. Schmidley

Richard J. Schmidley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020100958
    Abstract: A vertical fuse structure and methods for customization of integrated circuits include a substantially vertically-oriented interconnect structure or “fuse” which provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, a vertical interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second interconnect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 1, 2002
    Applicant: CLEAR LOGIC, INC.
    Inventors: John MacPherson, Alan H. Huggins, Richard J. Schmidley
  • Patent number: 6369437
    Abstract: A vertical fuse structure and methods for customization of integrated circuits include a substantially vertically-oriented interconnect structure or “fuse” which provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, a vertical interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second interconnect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: April 9, 2002
    Assignee: Clear Logic, Inc.
    Inventors: John MacPherson, Alan H. Huggins, Richard J. Schmidley
  • Patent number: 5945238
    Abstract: A method is provided for making re-usable configuration masks by initially patterning a mask blank using precision mask-making tools. The mask is then covered with an opaque material, and desired configuration points for a particular ASIC are selected with a non-precision laser. After the particular configuration pattern is no longer needed, the remaining opaque material is removed. The mask can then be re-configured for a new design by covering the mask with a new layer of opaque material and selecting new configuration points. Such a mask reduces both time and costs for creating a set of mask designs because a single mask can be re-used for several different designs without the further need of precision mask-making tools.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: August 31, 1999
    Assignee: Clear Logic, Inc.
    Inventors: Alan H. Huggins, John MacPherson, Richard J. Schmidley