Abstract: Embodiments herein describe coupling traditional fan and shaper control along with aggregated knowledge of the temperature history of a hardware device to optimally manage the temperature of the hardware device to preserve its expected life while also providing the lower power, best performing solution possible. In one embodiment, a cooling application manages the expected life by trading off performance and power versus temperature to achieve a desired (or accepted) lifetime. In one embodiment, the cooling application calculates a historical temperature value for the hardware device which is then used to determine the expected life of the hardware device.

Abstract: Embodiments herein describe coupling traditional fan and shaper control along with aggregated knowledge of the temperature history of a hardware device to optimally manage the temperature of the hardware device to preserve its expected life while also providing the lower power, best performing solution possible. In one embodiment, a cooling application manages the expected life by trading off performance and power versus temperature to achieve a desired (or accepted) lifetime. In one embodiment, the cooling application calculates a historical temperature value for the hardware device which is then used to determine the expected life of the hardware device.

Abstract: Embodiments herein describe coupling traditional fan and shaper control along with aggregated knowledge of the temperature history of a hardware device to optimally manage the temperature of the hardware device to preserve its expected life while also providing the lower power, best performing solution possible. In one embodiment, a cooling application manages the expected life by trading off performance and power versus temperature to achieve a desired (or accepted) lifetime. In one embodiment, the cooling application calculates a historical temperature value for the hardware device which is then used to determine the expected life of the hardware device.

Abstract: Embodiments herein describe coupling traditional fan and shaper control along with aggregated knowledge of the temperature history of a hardware device to optimally manage the temperature of the hardware device to preserve its expected life while also providing the lower power, best performing solution possible. In one embodiment, a cooling application manages the expected life by trading off performance and power versus temperature to achieve a desired (or accepted) lifetime. In one embodiment, the cooling application calculates a historical temperature value for the hardware device which is then used to determine the expected life of the hardware device.

Abstract: Masks that selectively attenuate radiation for inspections of printed circuit boards (PCB) are disclosed. A PCB may be inspected for defects by exposing the PCB with radiation and analyzing the radiation transmitted through the PCB. By employing a radiation mask having first and second segments between the PCB and a radiation source, the radiation may be selectively attenuated to attenuate a first portion of the radiation with a first attenuation level to prevent performance degradation to sensitive semiconductor devices as part of a first sectional area of the PCB, and yet provide substantially non-attenuation or attenuation at a second attenuation level for a second portion of the radiation incident upon a second sectional area of the PCB which is free from sensitive semiconductor devices. In this manner, the selective attenuation enables inspection of the first and second sectional areas of the PCB without damage to the sensitive semiconductor devices.

Abstract: Masks that selectively attenuate radiation for inspections of printed circuit boards (PCB) are disclosed. A PCB may be inspected for defects by exposing the PCB with radiation and analyzing the radiation transmitted through the PCB. By employing a radiation mask having first and second segments between the PCB and a radiation source, the radiation may be selectively attenuated to attenuate a first portion of the radiation with a first attenuation level to prevent performance degradation to sensitive semiconductor devices as part of a first sectional area of the PCB, and yet provide substantially non-attenuation or attenuation at a second attenuation level for a second portion of the radiation incident upon a second sectional area of the PCB which is free from sensitive semiconductor devices. In this manner, the selective attenuation enables inspection of the first and second sectional areas of the PCB without damage to the sensitive semiconductor devices.

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.

Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metal plugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.

Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metalplugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.

Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: Critical programmed reliability of a metal-to-metal amorphous silicon antifuse is a function of programming current, operating current and total programming time. The time required to program a field programmable gate array is reduced by classifying antifuses to be programmed into three or more classes according to the amount of programming time required to achieve critical programmed reliability under programming current and operating current conditions. Each of these classes of antifuses is programmed with near the minimum programming time required to program every antifuse in the class to critical reliability. In this way, large numbers of antifuses are not programmed with significantly greater amounts of programming time than are actually required to program them to critical reliability. The time required to program the field programmable gate array is therefore reduced. Techniques for obtaining critical reliability data used in classifying antifuses are also disclosed.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.