Patents by Inventor Richard J. Wong

Richard J. Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190158921
    Abstract: Methods, apparatus, systems and articles of manufacture to assign viewers to media meter data are disclosed. An apparatus includes memory to store instructions, and a processor to execute the instructions to at least: determine first probabilities for first panelists in a media meter household during a first set of time periods, determine second probabilities for second panelists in a plurality of learning households during a second set of time periods, compare the first probabilities and the second probabilities to identify a candidate household from the plurality of learning households to associated with the media meter household, and impute ones of the first number of minutes to individual ones of the first panelists when second panelist behavior data associated with the candidate household indicates activity during one of the second set of time periods that matches activity in the media meter household during one of the first set of time periods.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Samantha M. Mowrer, Molly Poppie, Balachander Shankar, Ieok Hou Wong, Choongkoo Lee, Xiaoqi Cui, David J. Kurzynski, Richard Peters, Remy Spoentgen
  • Publication number: 20190154926
    Abstract: A protective assembly method using a transparent layer within the fiber interconnect system aids in optical coupling by preventing an air gap from forming between the fiber cores within a connector. A thin transparent film (or with adhesive) is placed over the fiber end-faces at the connector interface, the film having characteristics which allows it to conform to the fiber end and minimize coupling loss between fibers. The film is sized to fit connectors faces and can be temporary, being replaced with each installation. A coating can also applied to the connector surface, providing a similar effect, as well as structurally enhancing the connector surfaces.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 23, 2019
    Inventors: Charles B. Kuznia, Richard J. Pommer, Joseph F. Ahadian, Richard T. Hagan, Man W. Wong
  • Patent number: 10297061
    Abstract: A method and system for rendering graphics based on user customizations in a computer graphics application are disclosed. The customizations relate to various properties of one or more graphical elements in the graphic. Such properties include positioning, size, formatting and other visual attributes associated with the graphical elements. These properties may be defined as either semantic properties or presentation properties. Semantic properties are persistent across all graphic definitions. Presentation properties are specific to the graphic definition to which each particular graphic belongs. Thus, a customization to a semantic property of a displayed graphic is preserved in memory for application not only to the currently displayed graphic, but also to all other graphic definitions that may be displayed in the future. In contrast, a customization to a presentation property is only preserved for the currently displayed graphic, and thus not preserved for all other graphic definitions.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 21, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karen K. Wong, Scott A. Sherman, Dawn Wright, Matthew J. Kotler, Ilan Berker, Brent Gilbert, Cynthia C. Shelly, Gary A. Pritting, Kim Tapia St. Amant, Richard J. Wolf
  • Patent number: 9869643
    Abstract: Masks that selectively attenuate radiation for inspections of printed circuit boards (PCB) are disclosed. A PCB may be inspected for defects by exposing the PCB with radiation and analyzing the radiation transmitted through the PCB. By employing a radiation mask having first and second segments between the PCB and a radiation source, the radiation may be selectively attenuated to attenuate a first portion of the radiation with a first attenuation level to prevent performance degradation to sensitive semiconductor devices as part of a first sectional area of the PCB, and yet provide substantially non-attenuation or attenuation at a second attenuation level for a second portion of the radiation incident upon a second sectional area of the PCB which is free from sensitive semiconductor devices. In this manner, the selective attenuation enables inspection of the first and second sectional areas of the PCB without damage to the sensitive semiconductor devices.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: January 16, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: ShiJie Wen, Richard J. Wong
  • Publication number: 20150212217
    Abstract: Masks that selectively attenuate radiation for inspections of printed circuit boards (PCB) are disclosed. A PCB may be inspected for defects by exposing the PCB with radiation and analyzing the radiation transmitted through the PCB. By employing a radiation mask having first and second segments between the PCB and a radiation source, the radiation may be selectively attenuated to attenuate a first portion of the radiation with a first attenuation level to prevent performance degradation to sensitive semiconductor devices as part of a first sectional area of the PCB, and yet provide substantially non-attenuation or attenuation at a second attenuation level for a second portion of the radiation incident upon a second sectional area of the PCB which is free from sensitive semiconductor devices. In this manner, the selective attenuation enables inspection of the first and second sectional areas of the PCB without damage to the sensitive semiconductor devices.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: ShiJie WEN, Richard J. WONG
  • Patent number: 8547155
    Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 1, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: John C. Holst, ShiJie Wen, Richard J. Wong
  • Publication number: 20130049835
    Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: John C. Holst, ShiJie Wen, Richard J. Wong
  • Patent number: 7187228
    Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: March 6, 2007
    Assignee: Quicklogic Corporation
    Inventors: Rajiv Jain, Richard J. Wong
  • Patent number: 6577017
    Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metal plugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: June 10, 2003
    Assignee: Quick Logic Corporation
    Inventor: Richard J. Wong
  • Patent number: 6300688
    Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metalplugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: October 9, 2001
    Assignee: QuickLogic Corporation
    Inventor: Richard J. Wong
  • Patent number: 6140837
    Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: October 31, 2000
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Richard J. Wong, James M. Apland
  • Patent number: 6097077
    Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: August 1, 2000
    Assignee: Quicklogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong
  • Patent number: 6028444
    Abstract: Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: February 22, 2000
    Assignee: QuickLogic Corporation
    Inventors: Richard J. Wong, Paige A. Kolze
  • Patent number: 5880512
    Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: March 9, 1999
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong
  • Patent number: 5786268
    Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: July 28, 1998
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong
  • Patent number: 5701027
    Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: December 23, 1997
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong
  • Patent number: 5661412
    Abstract: Critical programmed reliability of a metal-to-metal amorphous silicon antifuse is a function of programming current, operating current and total programming time. The time required to program a field programmable gate array is reduced by classifying antifuses to be programmed into three or more classes according to the amount of programming time required to achieve critical programmed reliability under programming current and operating current conditions. Each of these classes of antifuses is programmed with near the minimum programming time required to program every antifuse in the class to critical reliability. In this way, large numbers of antifuses are not programmed with significantly greater amounts of programming time than are actually required to program them to critical reliability. The time required to program the field programmable gate array is therefore reduced. Techniques for obtaining critical reliability data used in classifying antifuses are also disclosed.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: August 26, 1997
    Assignee: QuickLogic Corporation
    Inventors: Amarpreet S. Chawla, Richard J. Wong, Andrew K. Chan
  • Patent number: 5557136
    Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: September 17, 1996
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong
  • Patent number: 5544070
    Abstract: A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: August 6, 1996
    Assignee: QuickLogic Corporation
    Inventors: William D. Cox, Andrew K. L. Chan, Richard J. Wong, James M. Apland, Kathryn E. Gordon
  • Patent number: 5362676
    Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: November 8, 1994
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong